1f016f8caSMarek Vasut /* 2f016f8caSMarek Vasut * Copyright 2011, Marvell Semiconductor Inc. 3f016f8caSMarek Vasut * 4f016f8caSMarek Vasut * Licensed under the GPL-2 or later. 5f016f8caSMarek Vasut */ 6f016f8caSMarek Vasut #ifndef __GADGET__CI_UDC_H__ 7f016f8caSMarek Vasut #define __GADGET__CI_UDC_H__ 8f016f8caSMarek Vasut 9f016f8caSMarek Vasut #define NUM_ENDPOINTS 6 10f016f8caSMarek Vasut 11fcf2ede1SStephen Warren #ifdef CONFIG_CI_UDC_HAS_HOSTPC 12f016f8caSMarek Vasut struct ci_udc { 13fcf2ede1SStephen Warren u32 usbcmd; /* 0x130 */ 14fcf2ede1SStephen Warren u32 usbsts; /* 0x134 */ 15fcf2ede1SStephen Warren u32 pad1[3]; 16fcf2ede1SStephen Warren u32 devaddr; /* 0x144 */ 17fcf2ede1SStephen Warren u32 epinitaddr; /* 0x148 */ 18fcf2ede1SStephen Warren u32 pad2[10]; 19fcf2ede1SStephen Warren u32 portsc; /* 0x174 */ 20fcf2ede1SStephen Warren u32 pad178[(0x1b4 - (0x174 + 4)) / 4]; 21fcf2ede1SStephen Warren u32 hostpc1_devlc; /* 0x1b4 */ 22fcf2ede1SStephen Warren u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4]; 23fcf2ede1SStephen Warren u32 usbmode; /* 0x1f8 */ 24fcf2ede1SStephen Warren u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4]; 25fcf2ede1SStephen Warren u32 epsetupstat; /* 0x208 */ 26fcf2ede1SStephen Warren u32 epprime; /* 0x20c */ 27fcf2ede1SStephen Warren u32 epflush; /* 0x210 */ 28fcf2ede1SStephen Warren u32 epstat; /* 0x214 */ 29fcf2ede1SStephen Warren u32 epcomp; /* 0x218 */ 30fcf2ede1SStephen Warren u32 epctrl[16]; /* 0x21c */ 31fcf2ede1SStephen Warren }; 32fcf2ede1SStephen Warren #else 33fcf2ede1SStephen Warren struct ci_udc { 34f016f8caSMarek Vasut u32 usbcmd; /* 0x140 */ 35f016f8caSMarek Vasut u32 usbsts; /* 0x144 */ 36f016f8caSMarek Vasut u32 pad1[3]; 37f016f8caSMarek Vasut u32 devaddr; /* 0x154 */ 38f016f8caSMarek Vasut u32 epinitaddr; /* 0x158 */ 39f016f8caSMarek Vasut u32 pad2[10]; 40f016f8caSMarek Vasut u32 portsc; /* 0x184 */ 41f016f8caSMarek Vasut u32 pad3[8]; 42f016f8caSMarek Vasut u32 usbmode; /* 0x1a8 */ 43f016f8caSMarek Vasut u32 epstat; /* 0x1ac */ 44f016f8caSMarek Vasut u32 epprime; /* 0x1b0 */ 45f016f8caSMarek Vasut u32 epflush; /* 0x1b4 */ 46f016f8caSMarek Vasut u32 pad4; 47f016f8caSMarek Vasut u32 epcomp; /* 0x1bc */ 48fcf2ede1SStephen Warren u32 epctrl[16]; /* 0x1c0 */ 49fcf2ede1SStephen Warren }; 50fcf2ede1SStephen Warren 51fcf2ede1SStephen Warren #define PTS_ENABLE 2 52fcf2ede1SStephen Warren #define PTS(x) (((x) & 0x3) << 30) 53fcf2ede1SStephen Warren #define PFSC (1 << 24) 54fcf2ede1SStephen Warren #endif 55fcf2ede1SStephen Warren 56fcf2ede1SStephen Warren #define MICRO_8FRAME 0x8 57fcf2ede1SStephen Warren #define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) 58fcf2ede1SStephen Warren #define USBCMD_FS2 (1 << 15) 59fcf2ede1SStephen Warren #define USBCMD_RST (1 << 1) 60fcf2ede1SStephen Warren #define USBCMD_RUN (1) 61fcf2ede1SStephen Warren 62fcf2ede1SStephen Warren #define STS_SLI (1 << 8) 63fcf2ede1SStephen Warren #define STS_URI (1 << 6) 64fcf2ede1SStephen Warren #define STS_PCI (1 << 2) 65fcf2ede1SStephen Warren #define STS_UEI (1 << 1) 66fcf2ede1SStephen Warren #define STS_UI (1 << 0) 67fcf2ede1SStephen Warren 68fcf2ede1SStephen Warren #define USBMODE_DEVICE 2 69fcf2ede1SStephen Warren 70fcf2ede1SStephen Warren #define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) 71fcf2ede1SStephen Warren #define EPT_RX(x) (1 << ((x) & 0xffff)) 72fcf2ede1SStephen Warren 73f016f8caSMarek Vasut #define CTRL_TXE (1 << 23) 74f016f8caSMarek Vasut #define CTRL_TXR (1 << 22) 75f016f8caSMarek Vasut #define CTRL_RXE (1 << 7) 76f016f8caSMarek Vasut #define CTRL_RXR (1 << 6) 77f016f8caSMarek Vasut #define CTRL_TXT_BULK (2 << 18) 78f016f8caSMarek Vasut #define CTRL_RXT_BULK (2 << 2) 79f016f8caSMarek Vasut 802813006fSStephen Warren struct ci_req { 812813006fSStephen Warren struct usb_request req; 822813006fSStephen Warren struct list_head queue; 832813006fSStephen Warren /* Bounce buffer allocated if needed to align the transfer */ 842813006fSStephen Warren uint8_t *b_buf; 852813006fSStephen Warren uint32_t b_len; 862813006fSStephen Warren /* Buffer for the current transfer. Either req.buf/len or b_buf/len */ 872813006fSStephen Warren uint8_t *hw_buf; 882813006fSStephen Warren uint32_t hw_len; 89*6a132416SSiva Durga Prasad Paladugu uint32_t dtd_count; 902813006fSStephen Warren }; 912813006fSStephen Warren 92f016f8caSMarek Vasut struct ci_ep { 93f016f8caSMarek Vasut struct usb_ep ep; 94f016f8caSMarek Vasut struct list_head queue; 952813006fSStephen Warren bool req_primed; 96f016f8caSMarek Vasut const struct usb_endpoint_descriptor *desc; 97f016f8caSMarek Vasut }; 98f016f8caSMarek Vasut 99f016f8caSMarek Vasut struct ci_drv { 100f016f8caSMarek Vasut struct usb_gadget gadget; 101a2d8f929SStephen Warren struct ci_req *ep0_req; 102006c7026SStephen Warren bool ep0_data_phase; 103f016f8caSMarek Vasut struct usb_gadget_driver *driver; 104f016f8caSMarek Vasut struct ehci_ctrl *ctrl; 105f016f8caSMarek Vasut struct ept_queue_head *epts; 106f016f8caSMarek Vasut uint8_t *items_mem; 107f016f8caSMarek Vasut struct ci_ep ep[NUM_ENDPOINTS]; 108f016f8caSMarek Vasut }; 109f016f8caSMarek Vasut 110f016f8caSMarek Vasut struct ept_queue_head { 111f016f8caSMarek Vasut unsigned config; 112f016f8caSMarek Vasut unsigned current; /* read-only */ 113f016f8caSMarek Vasut 114f016f8caSMarek Vasut unsigned next; 115f016f8caSMarek Vasut unsigned info; 116f016f8caSMarek Vasut unsigned page0; 117f016f8caSMarek Vasut unsigned page1; 118f016f8caSMarek Vasut unsigned page2; 119f016f8caSMarek Vasut unsigned page3; 120f016f8caSMarek Vasut unsigned page4; 121f016f8caSMarek Vasut unsigned reserved_0; 122f016f8caSMarek Vasut 123f016f8caSMarek Vasut unsigned char setup_data[8]; 124f016f8caSMarek Vasut 125f016f8caSMarek Vasut unsigned reserved_1; 126f016f8caSMarek Vasut unsigned reserved_2; 127f016f8caSMarek Vasut unsigned reserved_3; 128f016f8caSMarek Vasut unsigned reserved_4; 129f016f8caSMarek Vasut }; 130f016f8caSMarek Vasut 131f016f8caSMarek Vasut #define CONFIG_MAX_PKT(n) ((n) << 16) 132f016f8caSMarek Vasut #define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ 133f016f8caSMarek Vasut #define CONFIG_IOS (1 << 15) /* IRQ on setup */ 134f016f8caSMarek Vasut 135f016f8caSMarek Vasut struct ept_queue_item { 136f016f8caSMarek Vasut unsigned next; 137f016f8caSMarek Vasut unsigned info; 138f016f8caSMarek Vasut unsigned page0; 139f016f8caSMarek Vasut unsigned page1; 140f016f8caSMarek Vasut unsigned page2; 141f016f8caSMarek Vasut unsigned page3; 142f016f8caSMarek Vasut unsigned page4; 143f016f8caSMarek Vasut unsigned reserved; 144f016f8caSMarek Vasut }; 145f016f8caSMarek Vasut 146f016f8caSMarek Vasut #define TERMINATE 1 147f016f8caSMarek Vasut #define INFO_BYTES(n) ((n) << 16) 148f016f8caSMarek Vasut #define INFO_IOC (1 << 15) 149f016f8caSMarek Vasut #define INFO_ACTIVE (1 << 7) 150f016f8caSMarek Vasut #define INFO_HALTED (1 << 6) 151f016f8caSMarek Vasut #define INFO_BUFFER_ERROR (1 << 5) 152f016f8caSMarek Vasut #define INFO_TX_ERROR (1 << 3) 153f016f8caSMarek Vasut #endif 154