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/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
/openbmc/linux/arch/sh/boards/
H A Dboard-urquell.c32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
/openbmc/linux/arch/sh/include/cpu-sh4/cpu/
H A Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dhisilicon,fmc-spi-nor.txt7 - size-cells : Should be 0.
16 #size-cells = <0>;
17 reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
20 flash@0 {
22 reg = <0>;
H A Dnxp-spifi.txt5 mode 0 or 3. The controller operates in either command or memory
25 - spi-cpol : Controller only supports mode 0 and 3 so either
37 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
44 flash@0 {
52 partition@0 {
54 reg = <0 0x200000>;
/openbmc/linux/arch/mips/include/asm/mach-ar7/
H A Dspaces.h17 #define PAGE_OFFSET _AC(0x94000000, UL)
18 #define PHYS_OFFSET _AC(0x14000000, UL)
/openbmc/linux/drivers/input/serio/
H A Di8042-snirm.h26 #define I8042_COMMAND_REG (kbd_iobase + 0x64UL)
27 #define I8042_DATA_REG (kbd_iobase + 0x60UL)
31 return readb(kbd_iobase + 0x60UL); in i8042_read_data()
36 return readb(kbd_iobase + 0x64UL); in i8042_read_status()
41 writeb(val, kbd_iobase + 0x60UL); in i8042_write_data()
46 writeb(val, kbd_iobase + 0x64UL); in i8042_write_command()
52 kbd_iobase = ioremap(0x16000000, 4); in i8042_platform_init()
56 kbd_iobase = ioremap(0x14000000, 4); in i8042_platform_init()
63 return 0; in i8042_platform_init()
/openbmc/u-boot/doc/device-tree-bindings/mtd/
H A Daltera_qspi.txt11 - #size-cells: Must be <0>.
23 quadspi_controller_0: quadspi@0x180014a0 {
25 reg = <0x180014a0 0x00000020>,
26 <0x14000000 0x04000000>;
29 #size-cells = <0>;
30 flash0: epcq512@0 {
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,versatile-fpga-irq.txt18 the interrupts are valid. Unconnected/unused lines are set to 0, and
30 reg = <0x14000000 0x100>;
31 clear-mask = <0xffffffff>;
32 valid-mask = <0x003fffff>;
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
H A Dmacros.fuc25 #define GT215 0xa3
26 #define GF100 0xc0
27 #define GF119 0xd9
28 #define GK208 0x108
33 #define NV_PPWR_INTR_TRIGGER 0x0000
34 #define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
35 #define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
36 #define NV_PPWR_INTR_ACK 0x0004
37 #define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
38 #define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
[all …]
/openbmc/qemu/tests/qtest/
H A Dast2700-smc-test.c22 g_assert(fd >= 0); in test_ast2700_evb()
24 g_assert(ret == 0); in test_ast2700_evb()
32 data->flash_base = 0x100000000; in test_ast2700_evb()
33 data->spi_base = 0x14000000; in test_ast2700_evb()
34 data->jedec_id = 0xef4021; in test_ast2700_evb()
35 data->cs = 0; in test_ast2700_evb()
36 data->node = "/machine/soc/fmc/ssi.0/child[0]"; in test_ast2700_evb()
38 data->page_addr = 0x40000 * FLASH_PAGE_SIZE; in test_ast2700_evb()
/openbmc/u-boot/include/configs/
H A Dimx6dl-mamoj.h29 # define CONFIG_ENV_OFFSET 0x100000
35 "scriptaddr=0x14000000\0" \
36 "fdt_addr_r=0x13000000\0" \
37 "kernel_addr_r=0x10008000\0" \
38 "fdt_high=0xffffffff\0" \
39 "dfu_alt_info_spl=spl raw 0x2 0x400\0" \
40 "dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
62 #define CONFIG_MXC_USB_FLAGS 0
69 #define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
73 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
[all …]
H A Dkp_imx6q_tpc.h31 #define CONFIG_FEC_MXC_PHYADDR 0
49 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
51 #define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
65 #define CONFIG_MXC_USB_FLAGS 0
75 #define CONFIG_LOADADDR 0x12000000
80 "console=ttymxc0,115200\0" \
81 "fdt_addr=0x18000000\0" \
82 "fdt_high=0xffffffff\0" \
83 "initrd_high=0xffffffff\0" \
84 "kernel_addr_r=0x10008000\0" \
[all …]
H A Ddh_imx6.h17 * 0x00_0000-0x00_ffff ... U-Boot SPL
18 * 0x01_0000-0x0f_ffff ... U-Boot
19 * 0x10_0000-0x10_ffff ... U-Boot env #1
20 * 0x11_0000-0x11_ffff ... U-Boot env #2
21 * 0x12_0000-0x1f_ffff ... UNUSED
26 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
48 #define CONFIG_FEC_MXC_PHYADDR 0
66 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
73 #define CONFIG_DWC_AHSATA_PORT_ID 0
91 #define CONFIG_MXC_USB_FLAGS 0
[all …]
/openbmc/linux/arch/sh/include/mach-se/mach/
H A Dse7751.h19 #define PA_ROM 0x00000000 /* EPROM */
20 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
21 #define PA_FROM 0x01000000 /* EPROM */
22 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
23 #define PA_EXT1 0x04000000
24 #define PA_EXT1_SIZE 0x04000000
25 #define PA_EXT2 0x08000000
26 #define PA_EXT2_SIZE 0x04000000
27 #define PA_SDRAM 0x0c000000
28 #define PA_SDRAM_SIZE 0x04000000
[all …]
H A Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
H A Dse7343.h16 /* Area 0 */
17 #define PA_ROM 0x00000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
19 #define PA_FROM 0x00400000 /* Flash ROM */
20 #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
21 #define PA_SRAM 0x00800000 /* SRAM */
22 #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
24 #define PA_EXT1 0x04000000
25 #define PA_EXT1_SIZE 0x04000000
27 #define PA_EXT2 0x08000000
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
/openbmc/u-boot/drivers/net/fm/
H A Dls1043.c11 #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
12 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
13 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
14 #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
15 #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
16 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
17 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
18 #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
19 #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
H A Dls1046.c11 #define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
12 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
13 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
14 #define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
15 #define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
16 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
17 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
18 #define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
19 #define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mmsys.yaml18 pattern: "^syscon@[0-9a-f]+$"
107 reg = <0x14000000 0x1000>;
111 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
113 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl-evk.dts27 reg = <0x00000000 0x80000000 0 0x40000000>;
39 * reg = <0 0x96000000 0 0x2000000>;
48 size = <0 0x14000000>;
49 alloc-ranges = <0 0x98000000 0 0x14000000>;
54 mux3_en: regulator-0 {
78 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
119 pinctrl-0 = <&pinctrl_eqos>;
129 #size-cells = <0>;
131 ethphy0: ethernet-phy@0 {
133 reg = <0>;
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dwii.c22 #define EXI_CTRL HW_REG(0x0d800070)
23 #define EXI_CTRL_ENABLE (1<<0)
25 #define MEM2_TOP (0x10000000 + 64*1024*1024)
42 if (pa < 0x10000000 || pa > 0x14000000) in mipc_check_address()
44 return 0; in mipc_check_address()
52 hdrp = (struct mipc_infohdr **)0x13fffffc; in mipc_get_infohdr()
93 error = 0; in mipc_get_mem2_boundary()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h22 #define AR71XX_APB_BASE 0x18000000
23 #define AR71XX_GE0_BASE 0x19000000
24 #define AR71XX_GE0_SIZE 0x10000
25 #define AR71XX_GE1_BASE 0x1a000000
26 #define AR71XX_GE1_SIZE 0x10000
27 #define AR71XX_EHCI_BASE 0x1b000000
28 #define AR71XX_EHCI_SIZE 0x1000
29 #define AR71XX_OHCI_BASE 0x1c000000
30 #define AR71XX_OHCI_SIZE 0x1000
31 #define AR71XX_SPI_BASE 0x1f000000
[all …]

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