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/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dxusb-padctl.c17 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
22 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
24 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
27 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
32 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
37 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
39 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
41 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
94 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
95 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
[all …]
/openbmc/linux/drivers/clk/visconti/
H A Dclkc-tmpv770x.c35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c25 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
45 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
47 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
49 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
135 return 0; in tegra_xusb_padctl_get_group_pins()
151 #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-pcs-ufs-v3.h9 #define QPHY_V3_PCS_UFS_PHY_START 0x000
10 #define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004
11 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
12 #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
13 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
14 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
15 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
16 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
17 #define QPHY_V3_PCS_UFS_READY_STATUS 0x160
18 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
H A Dphy-qcom-qmp-qserdes-com-v3.h11 #define QSERDES_V3_COM_ATB_SEL1 0x000
12 #define QSERDES_V3_COM_ATB_SEL2 0x004
13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
14 #define QSERDES_V3_COM_BG_TIMER 0x00c
15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
18 #define QSERDES_V3_COM_SSC_PER1 0x01c
19 #define QSERDES_V3_COM_SSC_PER2 0x020
20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v5.h10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v4.h10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
/openbmc/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc_regs.h11 NOT_APPLICABLE_OFF = 0,
96 #define DISPC_VID_ACCUH_0 0x0
97 #define DISPC_VID_ACCUH_1 0x4
98 #define DISPC_VID_ACCUH2_0 0x8
99 #define DISPC_VID_ACCUH2_1 0xc
100 #define DISPC_VID_ACCUV_0 0x10
101 #define DISPC_VID_ACCUV_1 0x14
102 #define DISPC_VID_ACCUV2_0 0x18
103 #define DISPC_VID_ACCUV2_1 0x1c
104 #define DISPC_VID_ATTRIBUTES 0x20
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]
/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c21 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
22 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
24 #define FUSE_SKU_CALIB_HS_IREF_CAP_MASK 0x3
26 #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK 0x3
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
32 #define XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK 0x3
33 #define XUSB_PADCTL_USB2_PORT_CAP_DISABLED 0x0
34 #define XUSB_PADCTL_USB2_PORT_CAP_HOST 0x1
35 #define XUSB_PADCTL_USB2_PORT_CAP_DEVICE 0x2
[all …]
/openbmc/linux/drivers/soc/tegra/fuse/
H A Dspeedo-tegra114.c25 {0, UINT_MAX},
30 {0, UINT_MAX},
41 case 0x00: in rev_sku_to_speedo_ids()
42 case 0x10: in rev_sku_to_speedo_ids()
43 case 0x05: in rev_sku_to_speedo_ids()
44 case 0x06: in rev_sku_to_speedo_ids()
46 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids()
50 case 0x03: in rev_sku_to_speedo_ids()
51 case 0x04: in rev_sku_to_speedo_ids()
59 sku_info->cpu_speedo_id = 0; in rev_sku_to_speedo_ids()
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c644 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
646 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31),
650 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
651 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15),
652 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23),
653 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31),
655 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7),
656 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15),
657 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 16, 3, 23),
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/openbmc/linux/include/linux/mfd/
H A Didt82p33_reg.h10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
13 #define DPLL1_TOD_CNFG 0x134
14 #define DPLL2_TOD_CNFG 0x1B4
16 #define DPLL1_TOD_STS 0x10B
17 #define DPLL2_TOD_STS 0x18B
19 #define DPLL1_TOD_TRIGGER 0x115
20 #define DPLL2_TOD_TRIGGER 0x195
22 #define DPLL1_OPERATING_MODE_CNFG 0x120
23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dddr_defs.h17 #define VTP_CTRL_READY (0x1 << 5)
18 #define VTP_CTRL_ENABLE (0x1 << 6)
19 #define VTP_CTRL_START_EN (0x1)
21 #define DDR_CKE_CTRL_NORMAL 0x3
23 #define DDR_CKE_CTRL_NORMAL 0x1
25 #define PHY_EN_DYN_PWRDN (0x1 << 20)
28 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
29 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
30 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
31 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h22 u32 reserved[0x1a];
25 u32 reserved2[0x18];
34 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
50 u32 reserved6[0x0a];
52 u32 reserved7[0x14];
54 u32 reserved8[0x1d];
56 u32 reserved9[0x2b];
63 u32 reserved10[0x1a];
68 check_member(rk3399_cru, sdio1_con[1], 0x594);
/openbmc/u-boot/arch/arm/dts/
H A Dvf610-pinfunc.h18 #define ALT0 0x0
19 #define ALT1 0x1
20 #define ALT2 0x2
21 #define ALT3 0x3
22 #define ALT4 0x4
23 #define ALT5 0x5
24 #define ALT6 0x6
25 #define ALT7 0x7
28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
H A Dam335x-bone-common.dtsi11 cpu@0 {
23 reg = <0x80000000 0x10000000>; /* 256 MB */
28 pinctrl-0 = <&user_leds_s0>;
61 vmmcsd_fixed: fixedregulator@0 {
71 pinctrl-0 = <&clkout2_pin>;
75 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
76 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
77 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
78 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
84 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Dinput_formatter_local.h27 #define HIVE_IF_FSM_SYNC_STATUS 0x100
28 #define HIVE_IF_FSM_SYNC_COUNTER 0x104
29 #define HIVE_IF_FSM_DEINTERLEAVING_IDX 0x114
30 #define HIVE_IF_FSM_DECIMATION_H_COUNTER 0x118
31 #define HIVE_IF_FSM_DECIMATION_V_COUNTER 0x11C
32 #define HIVE_IF_FSM_DECIMATION_BLOCK_V_COUNTER 0x120
33 #define HIVE_IF_FSM_PADDING_STATUS 0x124
34 #define HIVE_IF_FSM_PADDING_ELEMENT_COUNTER 0x128
35 #define HIVE_IF_FSM_VECTOR_SUPPORT_ERROR 0x12C
36 #define HIVE_IF_FSM_VECTOR_SUPPORT_BUFF_FULL 0x130
[all …]
/openbmc/linux/drivers/usb/fotg210/
H A Dfotg210-udc.h14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]

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