/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-mt6795-topckgen.c | 17 * So we model these clocks' rate as 0, to denote it's not an actual rate. 19 #define DUMMY_RATE 0 23 (_reg + 0x4), (_reg + 0x8), _shift, _width, \ 24 _gate, 0, -1, _flags) 362 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0), 363 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0), 364 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0), 365 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0), 370 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0), 371 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0), [all …]
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H A D | clk-mt8173-topckgen.c | 18 * So we model these clocks' rate as 0, to denote it's not an actual rate. 20 #define DUMMY_RATE 0 24 (_reg + 0x4), (_reg + 0x8), _shift, _width, \ 25 _gate, 0, -1, _flags) 437 FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0), 438 FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0), 439 FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0), 440 FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0), 445 FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0), 446 FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0), [all …]
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/openbmc/linux/drivers/clk/visconti/ |
H A D | clkc-tmpv770x.c | 35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, }, 37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, }, 39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, }, 42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, }, 43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, }, 44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, }, 51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200, 55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20, 59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10, 63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4, [all …]
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/openbmc/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7623.c | 17 #define MT7623_CLKSQ_STB_CON0 0x18 18 #define MT7623_PLL_ISO_CON0 0x24 22 #define MCU_AXI_DIV 0x60 23 #define AXI_DIV_MSK GENMASK(4, 0) 44 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0, 45 21, 0x204, 24, 0x204, 0), 46 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR, 47 21, 0x210, 4, 0x214, 0), 48 PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR, 49 7, 0x220, 4, 0x224, 14), [all …]
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/openbmc/linux/drivers/media/pci/cx18/ |
H A D | cx18-av-audio.c | 60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq() 61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq() 63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq() 65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq() 66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq() 67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq() 69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq() 70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq() 71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq() 74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq() [all …]
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/openbmc/linux/drivers/clk/sunxi-ng/ |
H A D | ccu-sun50i-h6-r.c | 29 { .index = 3, .shift = 0, .width = 5 }, 44 .reg = 0x000, 49 0), 53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0); 55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0); 69 .reg = 0x010, 74 0), 86 0x11c, BIT(0), 0); 88 0x12c, BIT(0), 0); 90 0x13c, BIT(0), 0); [all …]
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H A D | ccu-sun20i-d1-r.c | 26 r_ahb_apb0_parents, 0x000, 27 0, 5, /* M */ 30 0); 34 r_ahb_apb0_parents, 0x00c, 35 0, 5, /* M */ 38 0); 42 0x11c, BIT(0), 0); 44 0x12c, BIT(0), 0); 46 0x1ac, BIT(0), 0); 53 r_ir_rx_parents, 0x1c0, [all …]
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-qserdes-txrx-v4.h | 10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11 #define QSERDES_V4_TX_BIST_INVERT 0x004 12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014 16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 19 #define QSERDES_V4_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5.h | 11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 12 #define QSERDES_V5_TX_BIST_INVERT 0x004 13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c 15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014 17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c 19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 20 #define QSERDES_V5_TX_TX_BAND 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-pll.h | 10 #define QSERDES_PLL_BG_TIMER 0x00c 11 #define QSERDES_PLL_SSC_PER1 0x01c 12 #define QSERDES_PLL_SSC_PER2 0x020 13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 18 #define QSERDES_PLL_CLK_ENABLE1 0x040 19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044 [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5_20.h | 10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80 15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90 16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0 17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc 20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c [all …]
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H A D | phy-qcom-qmp-qserdes-com-v3.h | 11 #define QSERDES_V3_COM_ATB_SEL1 0x000 12 #define QSERDES_V3_COM_ATB_SEL2 0x004 13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008 14 #define QSERDES_V3_COM_BG_TIMER 0x00c 15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 18 #define QSERDES_V3_COM_SSC_PER1 0x01c 19 #define QSERDES_V3_COM_SSC_PER2 0x020 20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 [all …]
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/openbmc/linux/drivers/soc/tegra/fuse/ |
H A D | fuse-tegra30.c | 21 #define FUSE_BEGIN 0x100 24 #define FUSE_VENDOR_CODE 0x100 25 #define FUSE_FAB_CODE 0x104 26 #define FUSE_LOT_CODE_0 0x108 27 #define FUSE_LOT_CODE_1 0x10c 28 #define FUSE_WAFER_ID 0x110 29 #define FUSE_X_COORDINATE 0x114 30 #define FUSE_Y_COORDINATE 0x118 32 #define FUSE_HAS_REVISION_INFO BIT(0) 45 return 0; in tegra30_fuse_read_early() [all …]
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H A D | speedo-tegra114.c | 25 {0, UINT_MAX}, 30 {0, UINT_MAX}, 41 case 0x00: in rev_sku_to_speedo_ids() 42 case 0x10: in rev_sku_to_speedo_ids() 43 case 0x05: in rev_sku_to_speedo_ids() 44 case 0x06: in rev_sku_to_speedo_ids() 46 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids() 50 case 0x03: in rev_sku_to_speedo_ids() 51 case 0x04: in rev_sku_to_speedo_ids() 59 sku_info->cpu_speedo_id = 0; in rev_sku_to_speedo_ids() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | qcom,ipq5332-usb-hsphy.yaml | 23 const: 0 49 reg = <0x0007b000 0x12c>; 54 #phy-cells = <0>;
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/openbmc/linux/drivers/video/fbdev/ |
H A D | wm8505fb_regs.h | 15 * Color space select register, default value 0x1c 22 #define WMT_GOVR_COLORSPACE 0x1e4 28 #define WMT_GOVR_COLORSPACE1 0x30 30 #define WMT_GOVR_CONTRAST 0x1b8 31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */ 34 #define WMT_GOVR_FBADDR 0x90 35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */ 38 #define WMT_GOVR_XPAN 0xa4 39 #define WMT_GOVR_YPAN 0xa0 41 #define WMT_GOVR_XRES 0x98 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | vf610-pinfunc.h | 18 #define ALT0 0x0 19 #define ALT1 0x1 20 #define ALT2 0x2 21 #define ALT3 0x3 22 #define ALT4 0x4 23 #define ALT5 0x5 24 #define ALT6 0x6 25 #define ALT7 0x7 28 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 29 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/linux/arch/arm/mach-davinci/ |
H A D | clock.h | 13 #define PLLCTL 0x100 14 #define PLLCTL_PLLEN BIT(0) 21 #define PLLM 0x110 22 #define PLLM_PLLM_MASK 0xff 24 #define PREDIV 0x114 25 #define PLLDIV1 0x118 26 #define PLLDIV2 0x11c 27 #define PLLDIV3 0x120 28 #define POSTDIV 0x128 29 #define BPDIV 0x12c [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-hi3798cv200/ |
H A D | hi3798cv200.h | 10 #define REG_BASE_PERI_CTRL 0xF8A20000 11 #define REG_BASE_CRG 0xF8A22000 14 #define REG_BASE_UART0 0xF8B00000 15 #define HIOTG_BASE_ADDR 0xF98C0000 19 #define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) 22 #define PERI_CTRL_USB3 (REG_BASE_PERI_CTRL + 0x12c) 27 #define PERI_CRG46 (REG_BASE_CRG + 0xb8) 28 #define USB2_BUS_CKEN (1<<0) 41 #define PERI_CRG47 (REG_BASE_CRG + 0xbc) 42 #define USB2_PHY01_REF_CKEN (1 << 0)
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-meson/ |
H A D | clock-axg.h | 18 #define HHI_GP0_PLL_CNTL 0x40 19 #define HHI_GP0_PLL_CNTL2 0x44 20 #define HHI_GP0_PLL_CNTL3 0x48 21 #define HHI_GP0_PLL_CNTL4 0x4c 22 #define HHI_GP0_PLL_CNTL5 0x50 23 #define HHI_GP0_PLL_STS 0x54 24 #define HHI_GP0_PLL_CNTL1 0x58 25 #define HHI_HIFI_PLL_CNTL 0x80 26 #define HHI_HIFI_PLL_CNTL2 0x84 27 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]
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/openbmc/linux/drivers/clk/meson/ |
H A D | axg.h | 19 #define HHI_GP0_PLL_CNTL 0x40 20 #define HHI_GP0_PLL_CNTL2 0x44 21 #define HHI_GP0_PLL_CNTL3 0x48 22 #define HHI_GP0_PLL_CNTL4 0x4c 23 #define HHI_GP0_PLL_CNTL5 0x50 24 #define HHI_GP0_PLL_STS 0x54 25 #define HHI_GP0_PLL_CNTL1 0x58 26 #define HHI_HIFI_PLL_CNTL 0x80 27 #define HHI_HIFI_PLL_CNTL2 0x84 28 #define HHI_HIFI_PLL_CNTL3 0x88 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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/openbmc/u-boot/board/xilinx/zynqmp/ |
H A D | zynqmp.c | 42 .id = 0x10, 46 .id = 0x10, 47 .ver = 0x2c, 51 .id = 0x11, 55 .id = 0x11, 56 .ver = 0x2c, 60 .id = 0x20, 65 .id = 0x20, 66 .ver = 0x100, 71 .id = 0x20, [all …]
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