Home
last modified time | relevance | path

Searched +full:0 +full:x118 (Results 1 – 25 of 486) sorted by relevance

12345678910>>...20

/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
18 #define PIO_IFER 0x20 /* Glitch Input Filter Enable */
19 #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
20 #define PIO_IFSR 0x28 /* Glitch Input Filter Status */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
[all …]
/openbmc/linux/drivers/crypto/
H A Datmel-tdes-regs.h5 #define TDES_CR 0x00
6 #define TDES_CR_START (1 << 0)
10 #define TDES_MR 0x04
11 #define TDES_MR_CYPHER_DEC (0 << 0)
12 #define TDES_MR_CYPHER_ENC (1 << 0)
13 #define TDES_MR_TDESMOD_MASK (0x3 << 1)
14 #define TDES_MR_TDESMOD_DES (0x0 << 1)
15 #define TDES_MR_TDESMOD_TDES (0x1 << 1)
16 #define TDES_MR_TDESMOD_XTEA (0x2 << 1)
17 #define TDES_MR_KEYMOD_3KEY (0 << 4)
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-com.h10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-matrix.h11 #define AT91SAM9260_MATRIX_MCFG 0x00
12 #define AT91SAM9260_MATRIX_SCFG 0x40
13 #define AT91SAM9260_MATRIX_PRS 0x80
14 #define AT91SAM9260_MATRIX_MRCR 0x100
15 #define AT91SAM9260_MATRIX_EBICSA 0x11c
17 #define AT91SAM9261_MATRIX_MRCR 0x0
18 #define AT91SAM9261_MATRIX_SCFG 0x4
19 #define AT91SAM9261_MATRIX_TCR 0x24
20 #define AT91SAM9261_MATRIX_EBICSA 0x30
21 #define AT91SAM9261_MATRIX_USBPUCR 0x34
[all …]
/openbmc/qemu/pc-bios/s390-ccw/
H A Ds390-arch.h28 #define PSW_MASK_IOINT 0x0200000000000000ULL
29 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
30 #define PSW_MASK_WAIT 0x0002000000000000ULL
31 #define PSW_MASK_EAMODE 0x0000000100000000ULL
32 #define PSW_MASK_BAMODE 0x0000000080000000ULL
33 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
39 PSWLegacy ipl_psw; /* 0x000 */
40 uint32_t ccw1[2]; /* 0x008 */
42 uint32_t ccw2[2]; /* 0x010 */
48 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dga102.c30 return !!(nvkm_falcon_rd32(falcon, 0x118) & 0x00000002); in ga102_flcn_dma_done()
36 nvkm_falcon_wr32(falcon, 0x114, mem_base); in ga102_flcn_dma_xfer()
37 nvkm_falcon_wr32(falcon, 0x11c, dma_base); in ga102_flcn_dma_xfer()
38 nvkm_falcon_wr32(falcon, 0x118, cmd); in ga102_flcn_dma_xfer()
47 *cmd |= 0x00000010; in ga102_flcn_dma_init()
49 *cmd |= 0x00000004; in ga102_flcn_dma_init()
51 nvkm_falcon_wr32(falcon, 0x110, dma_addr >> 8); in ga102_flcn_dma_init()
52 nvkm_falcon_wr32(falcon, 0x128, 0x00000000); in ga102_flcn_dma_init()
53 return 0; in ga102_flcn_dma_init()
66 nvkm_falcon_mask(falcon, 0x040, 0x00000000, 0x00000000); in ga102_flcn_reset_wait_mem_scrubbing()
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm21664.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 secondary-boot-reg = <0x35004178>;
41 #address-cells = <0>;
43 reg = <0x3ff01000 0x1000>,
44 <0x3ff00100 0x100>;
49 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
54 reg = <0x3e000000 0x118>;
64 reg = <0x3e001000 0x118>;
[all …]
H A Dbcm23550.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
60 secondary-boot-reg = <0x35004178>;
69 secondary-boot-reg = <0x35004178>;
78 secondary-boot-reg = <0x35004178>;
87 ranges = <0 0x34000000 0x102f83ac>;
93 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
98 reg = <0x01001f00 0x24>;
103 reg = <0x01003000 0x524>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-single.yaml48 const: 0
99 '-pins(-[0-9]+)?$|-pin$':
186 reg = <0x4a100040 0x0196>;
188 #size-cells = <0>;
193 pinctrl-single,function-mask = <0xffff>;
194 pinctrl-single,gpio-range = <&range 0 3 0>;
201 <0xd8 0x118>,
202 <0xda 0>,
203 <0xdc 0x118>,
204 <0xde 0>;
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pdc.h10 u32 rpr; /* 0x100 Receive Pointer Register */
11 u32 rcr; /* 0x104 Receive Counter Register */
12 u32 tpr; /* 0x108 Transmit Pointer Register */
13 u32 tcr; /* 0x10C Transmit Counter Register */
14 u32 pnpr; /* 0x110 Receive Next Pointer Register */
15 u32 pncr; /* 0x114 Receive Next Counter Register */
16 u32 tnpr; /* 0x118 Transmit Next Pointer Register */
17 u32 tncr; /* 0x11C Transmit Next Counter Register */
18 u32 ptcr; /* 0x120 Transfer Control Register */
19 u32 ptsr; /* 0x124 Transfer Status Register */
/openbmc/u-boot/arch/arc/cpu/arcv1/
H A Divt.S10 j _start /* 0 - 0x000 */
11 j memory_error /* 1 - 0x008 */
12 j instruction_error /* 2 - 0x010 */
16 j interrupt_handler /* 3:31 - 0x018:0xF8 */
19 j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
20 j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
21 j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
22 j EV_TLBProtV /* 0x118, Protection Violation (0x23)
24 j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
25 j EV_Trap /* 0x128, Trap exception (0x25) */
[all …]
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_exar_st16c554.c16 SERIAL8250_PORT(0x100, 5),
17 SERIAL8250_PORT(0x108, 5),
18 SERIAL8250_PORT(0x110, 5),
19 SERIAL8250_PORT(0x118, 5),
H A D8250_boca.c13 SERIAL8250_PORT(0x100, 12),
14 SERIAL8250_PORT(0x108, 12),
15 SERIAL8250_PORT(0x110, 12),
16 SERIAL8250_PORT(0x118, 12),
17 SERIAL8250_PORT(0x120, 12),
18 SERIAL8250_PORT(0x128, 12),
19 SERIAL8250_PORT(0x130, 12),
20 SERIAL8250_PORT(0x138, 12),
21 SERIAL8250_PORT(0x140, 12),
22 SERIAL8250_PORT(0x148, 12),
[all …]
/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-minix-neo.c14 { 0x118, KEY_POWER },
16 { 0x146, KEY_UP },
17 { 0x116, KEY_DOWN },
18 { 0x147, KEY_LEFT },
19 { 0x115, KEY_RIGHT },
20 { 0x155, KEY_ENTER },
22 { 0x110, KEY_VOLUMEDOWN },
23 { 0x140, KEY_BACK },
24 { 0x114, KEY_VOLUMEUP },
26 { 0x10d, KEY_HOME },
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dcpu.c20 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118); in s3c64xx_init_cpu()
26 writel_relaxed(0x0, S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
27 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
30 pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id); in s3c64xx_init_cpu()
/openbmc/linux/include/linux/
H A Datmel_pdc.h15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Dutil_csr.h10 #define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
11 #define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
12 #define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
14 #define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
16 #define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
17 #define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
18 #define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
19 #define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
21 #define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
22 #define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/openbmc/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_rdma.h10 #define MDP_RDMA_EN 0x000
11 #define MDP_RDMA_RESET 0x008
12 #define MDP_RDMA_CON 0x020
13 #define MDP_RDMA_GMCIF_CON 0x028
14 #define MDP_RDMA_SRC_CON 0x030
15 #define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
16 #define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
17 #define MDP_RDMA_MF_SRC_SIZE 0x070
18 #define MDP_RDMA_MF_CLIP_SIZE 0x078
19 #define MDP_RDMA_MF_OFFSET_1 0x080
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dwm8505fb_regs.h15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dclock.h13 #define PLLCTL 0x100
14 #define PLLCTL_PLLEN BIT(0)
21 #define PLLM 0x110
22 #define PLLM_PLLM_MASK 0xff
24 #define PREDIV 0x114
25 #define PLLDIV1 0x118
26 #define PLLDIV2 0x11c
27 #define PLLDIV3 0x120
28 #define POSTDIV 0x128
29 #define BPDIV 0x12c
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.h13 #define PCIECR 0xFE000008
14 #define PCIECR_ENBL 0x01
17 #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
18 #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
20 #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
23 #define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
24 #define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
25 #define SH7780_PCIAIR 0x11C /* Error Address Register */
26 #define SH7780_PCICIR 0x120 /* Error Command/Data Register */
27 #define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
[all …]

12345678910>>...20