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/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt8195-sys-clock.yaml53 reg = <0x10000000 0x1000>;
60 reg = <0x10001000 0x1000>;
67 reg = <0x1000c000 0x1000>;
74 reg = <0x11003000 0x1000>;
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt6582.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x2>;
37 reg = <0x3>;
44 #clock-cells = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
61 reg = <0x10008000 0x80>;
[all …]
H A Dmt6592.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
29 reg = <0x1>;
34 reg = <0x2>;
39 reg = <0x3>;
44 reg = <0x4>;
49 reg = <0x5>;
54 reg = <0x6>;
59 reg = <0x7>;
[all …]
H A Dmt8127.dtsi19 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
30 reg = <0x1>;
35 reg = <0x2>;
40 reg = <0x3>;
52 reg = <0 0x80002000 0 0x1000>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
[all …]
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
H A Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
H A Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6755.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0x000>;
36 reg = <0x001>;
43 reg = <0x002>;
50 reg = <0x003>;
57 reg = <0x100>;
64 reg = <0x101>;
71 reg = <0x102>;
78 reg = <0x103>;
[all …]
H A Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
H A Dmt6797.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]
H A Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
H A Dmt8365.dtsi21 #size-cells = <0>;
23 cluster0_opp: opp-table-0 {
125 cpu0: cpu@0 {
128 reg = <0x0>;
132 i-cache-size = <0x8000>;
135 d-cache-size = <0x8000>;
148 reg = <0x1>;
152 i-cache-size = <0x8000>;
155 d-cache-size = <0x8000>;
168 reg = <0x2>;
[all …]
H A Dmt6795.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
35 reg = <0x000>;
44 reg = <0x001>;
59 reg = <0x002>;
74 reg = <0x003>;
89 reg = <0x100>;
104 reg = <0x101>;
119 reg = <0x102>;
134 reg = <0x103>;
[all …]
H A Dmt7622.dtsi69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
140 reg = <0 0x43000000 0 0x30000>;
150 thermal-sensors = <&thermal 0>;
216 reg = <0 0x10000000 0 0x1000>;
223 reg = <0 0x10001000 0 0x250>;
[all …]
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
H A Dmt8192.dtsi34 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #clock-cells = <0>;
57 #size-cells = <0>;
59 cpu0: cpu@0 {
62 reg = <0x000>;
73 performance-domains = <&performance 0>;
80 reg = <0x100>;
91 performance-domains = <&performance 0>;
98 reg = <0x200>;
[all …]
H A Dmt8186.dtsi327 #size-cells = <0>;
365 cpu0: cpu@0 {
368 reg = <0x000>;
392 reg = <0x100>;
416 reg = <0x200>;
440 reg = <0x300>;
464 reg = <0x400>;
488 reg = <0x500>;
512 reg = <0x600>;
536 reg = <0x700>;
[all …]
H A Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
[all …]
H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-bluetooth.txt22 reg = <0 0x1100c000 0 0x1000>;
58 - pinctrl-0: Should contain UART RXD low when the device is powered up to
69 - pinctrl-0: Should contain UART mode pin ctrl
101 reg = <0 0x11003000 0 0x400>;
112 pinctrl-0 = <&uart1_pins_boot>;
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
40 reg = <0x1>;
50 reg = <0x2>;
60 reg = <0x3>;
71 #clock-cells = <0>;
76 #clock-cells = <0>;
81 clk26m: oscillator-0 {
83 #clock-cells = <0>;
[all …]
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0x0>;
37 reg = <0x1>;
42 clk20m: oscillator@0 {
44 #clock-cells = <0>;
51 #clock-cells = <0>;
69 reg = <0x10000000 0x1000>;
76 reg = <0x10002000 0x1000>;
83 reg = <0x10004000 0x80>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi17 #size-cells = <0>;
54 reg = <0x0 0x530000>;
62 reg = <0x0 0x530001>;
70 reg = <0x0 0x530002>;
78 reg = <0x0 0x530003>;
86 reg = <0x0 0x530100>;
94 reg = <0x0 0x530101>;
102 reg = <0x0 0x530102>;
110 reg = <0x0 0x530103>;
125 arm,psci-suspend-param = <0x00010002>;
[all …]