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/openbmc/linux/tools/testing/selftests/bpf/verifier/
H A Datomic_and.c4 /* val = 0x110; */
5 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
6 /* atomic_and(&val, 0x011); */
7 BPF_MOV64_IMM(BPF_REG_1, 0x011),
9 /* if (val != 0x010) exit(2); */
11 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x010, 2),
15 BPF_MOV64_IMM(BPF_REG_0, 0),
16 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
26 /* val = 0x110; */
27 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
[all …]
H A Datomic_xor.c4 /* val = 0x110; */
5 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
6 /* atomic_xor(&val, 0x011); */
7 BPF_MOV64_IMM(BPF_REG_1, 0x011),
9 /* if (val != 0x101) exit(2); */
11 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x101, 2),
15 BPF_MOV64_IMM(BPF_REG_0, 0),
16 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
26 /* val = 0x110; */
27 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
[all …]
H A Datomic_or.c4 /* val = 0x110; */
5 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
6 /* atomic_or(&val, 0x011); */
7 BPF_MOV64_IMM(BPF_REG_1, 0x011),
9 /* if (val != 0x111) exit(2); */
11 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x111, 2),
15 BPF_MOV64_IMM(BPF_REG_0, 0),
16 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
26 /* val = 0x110; */
27 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi22 reg = <0x45000000 0x00400000>;
28 reg = <0x44000000 0x01000000>;
35 #size-cells = <0>;
36 cpu@0 {
39 reg = <0>;
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dstih407-family.dtsi25 reg = <0x44000000 0x01000000>;
32 #size-cells = <0>;
33 cpu@0 {
36 reg = <0>;
38 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
39 cpu-release-addr = <0x94100A4>;
42 operating-points = <1500000 0
43 1200000 0
44 800000 0
45 500000 0>;
[all …]
/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Datomics.c13 __u32 pid = 0;
16 __u64 add64_result = 0;
18 __u32 add32_result = 0;
19 __u64 add_stack_value_copy = 0;
20 __u64 add_stack_result = 0;
27 return 0; in add()
38 return 0; in add()
42 __s64 sub64_result = 0;
44 __s32 sub32_result = 0;
45 __s64 sub_stack_value_copy = 0;
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dhpet.h11 #define HPET_ID 0x000
12 #define HPET_PERIOD 0x004
13 #define HPET_CFG 0x010
14 #define HPET_STATUS 0x020
15 #define HPET_COUNTER 0x0f0
17 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
18 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
19 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
21 #define HPET_T0_CFG 0x100
22 #define HPET_T0_CMP 0x108
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dcompat.h24 #define COMPAT_RLIM_INFINITY 0x7fffffff
28 #define COMPAT_UTS_MACHINE "sparc\0\0"
154 /* Vector 0x110 is LINUX_32BIT_SYSCALL_TRAP */ in in_compat_syscall()
155 return pt_regs_trap_type(current_pt_regs()) == 0x110; in in_compat_syscall()
/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
42 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
45 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
51 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
57 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
63 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
/openbmc/linux/Documentation/translations/zh_CN/core-api/
H A Dprintk-formats.rst115 %pS versatile_init+0x0/0x110
117 %pSR versatile_init+0x9/0x110
119 %pB prev_fn_of_versatile_init+0x88/0x88
133 %pS versatile_init+0x0/0x110 [module_name]
134 %pSb versatile_init+0x0/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
135 %pSRb versatile_init+0x9/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
137 %pBb prev_fn_of_versatile_init+0x88/0x88 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
195 %pr [mem 0x60000000-0x6fffffff flags 0x2200] or
196 [mem 0x0000000060000000-0x000000006fffffff flags 0x2200]
197 %pR [mem 0x60000000-0x6fffffff pref] or
[all …]
/openbmc/linux/tools/testing/selftests/bpf/prog_tests/
H A Datomics.c70 ASSERT_EQ(skel->data->and64_value, 0x010ull << 32, "and64_value"); in test_and()
71 ASSERT_EQ(skel->bss->and64_result, 0x110ull << 32, "and64_result"); in test_and()
73 ASSERT_EQ(skel->data->and32_value, 0x010, "and32_value"); in test_and()
74 ASSERT_EQ(skel->bss->and32_result, 0x110, "and32_result"); in test_and()
76 ASSERT_EQ(skel->data->and_noreturn_value, 0x010ull << 32, "and_noreturn_value"); in test_and()
92 ASSERT_EQ(skel->data->or64_value, 0x111ull << 32, "or64_value"); in test_or()
93 ASSERT_EQ(skel->bss->or64_result, 0x110ull << 32, "or64_result"); in test_or()
95 ASSERT_EQ(skel->data->or32_value, 0x111, "or32_value"); in test_or()
96 ASSERT_EQ(skel->bss->or32_result, 0x110, "or32_result"); in test_or()
98 ASSERT_EQ(skel->data->or_noreturn_value, 0x111ull << 32, "or_noreturn_value"); in test_or()
[all …]
/openbmc/linux/drivers/media/usb/stk1160/
H A Dstk1160-reg.h14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
/openbmc/u-boot/drivers/reset/
H A Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
46 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
47 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */
48 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
49 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
54 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
55 UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */
56 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
[all …]
/openbmc/qemu/pc-bios/s390-ccw/
H A Ds390-arch.h28 #define PSW_MASK_IOINT 0x0200000000000000ULL
29 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
30 #define PSW_MASK_WAIT 0x0002000000000000ULL
31 #define PSW_MASK_EAMODE 0x0000000100000000ULL
32 #define PSW_MASK_BAMODE 0x0000000080000000ULL
33 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
39 PSWLegacy ipl_psw; /* 0x000 */
40 uint32_t ccw1[2]; /* 0x008 */
42 uint32_t ccw2[2]; /* 0x010 */
48 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/openbmc/qemu/linux-user/loongarch64/
H A Dvdso-asmoffset.h1 #define sizeof_rt_sigframe 0x240
2 #define sizeof_sigcontext 0x110
3 #define sizeof_sctx_info 0x10
5 #define offsetof_sigcontext 0x130
6 #define offsetof_sigcontext_pc 0
8 #define offsetof_fpucontext_fr 0
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dclock.json8 "EventCode": "0x101",
14 "EventCode": "0x110",
/openbmc/linux/Documentation/scsi/
H A Dadvansys.rst90 default the debug level is 0.
96 'deb' and the fourth hex digit specifies the debug level: 0 - F.
97 The following command line will look for an adapter at 0x330
100 linux advansys=0x330,0,0,0,0xdeb2
112 0 Errors Only
141 syscall(103, 7, 0, 0);
163 /proc/scsi/advansys/{0,1,2,3,...}
167 cat /proc/scsi/advansys/0
192 boot: linux advansys=0x0
198 linux advansys=0x110
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c32 * [5:0]: Number of NOPs or registers to set values to in case of
37 * is used for offsets smaller than 0x200 while the latter is for values bigger
42 * [6:0]: Register offset, without considering the engine base.
53 #define POSTED BIT(0) in set_offsets()
54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
56 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
57 (((x) >> 2) & 0x7f) in set_offsets()
58 #define END 0 in set_offsets()
71 count = *data & 0x3f; in set_offsets()
84 u32 offset = 0; in set_offsets()
[all …]
/openbmc/linux/arch/arm/mach-orion5x/
H A Dbridge-regs.h9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
14 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
22 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]

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