Searched +full:0 +full:x10500000 (Results 1 – 14 of 14) sorted by relevance
54 reg = <0x52800000 0x100000>;59 #size-cells = <0>;60 cros-ec@0 {62 reg = <0>;63 interrupts = <93 0>;72 reg = <0x0 0x10500000 0x80000>;
114 reg = <0x10500000 0x80000>,115 <0x10700000 0x8000>,116 <0x10720000 0xe0000>;
38 #define EXYNOS4210_DRAM0_BASE_ADDR 0x4000000039 #define EXYNOS4210_DRAM1_BASE_ADDR 0xa000000040 #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */42 #define EXYNOS4210_IROM_BASE_ADDR 0x0000000043 #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */44 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x0200000045 #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */47 #define EXYNOS4210_IRAM_BASE_ADDR 0x0202000048 #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */52 #define EXYNOS4210_SMP_BOOT_SIZE 0x1000[all …]
20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */29 #define AR2315_MISC_IRQ_UART0 043 #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */44 #define AR2315_SPI_READ_SIZE 0x0100000045 #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */46 #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */[all …]
35 #clock-cells = <0>;41 reg = <0x10090000 0x10000>;52 reg = <0x10104000 0x800>;64 reg = <0x10138000 0x1000>;71 reg = <0x1013c000 0x100>;76 reg = <0x1013c200 0x20>;90 reg = <0x1013c600 0x20>;99 reg = <0x1013d000 0x1000>,100 <0x1013c100 0x0100>;105 reg = <0x10124000 0x400>;[all …]
34 #size-cells = <0>;40 reg = <0xf00>;53 reg = <0xf01>;84 #clock-cells = <0>;89 reg = <0x10080000 0x2000>;92 ranges = <0 0x10080000 0x2000>;94 smp-sram@0 {96 reg = <0x00 0x10>;102 reg = <0x10090000 0x10000>;122 reg = <0x10108000 0x800>;[all …]
29 #size-cells = <0>;34 reg = <0xf00>;47 reg = <0xf01>;53 reg = <0xf02>;59 reg = <0xf03>;77 #clock-cells = <0>;82 reg = <0x100a0000 0x1000>;87 reg = <0x10139000 0x1000>,88 <0x1013a000 0x1000>,89 <0x1013c000 0x2000>,[all …]
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */[all …]
39 reg = <0x60000000 0x40000000>;52 #size-cells = <0>;55 cpu0:cpu@0x000 {58 reg = <0x000>;68 cpu1:cpu@0x001 {71 reg = <0x001>;74 cpu2:cpu@0x002 {77 reg = <0x002>;80 cpu3:cpu@0x003 {83 reg = <0x003>;[all …]
68 reg = <0x03810000 0x0c>;79 reg = <0x03830000 0x100>;88 samsung,idma-addr = <0x03000000>;95 reg = <0x10000000 0x100>;100 reg = <0x10500000 0x2000>;105 reg = <0x12570000 0x14>;110 reg = <0x10023c40 0x20>;111 #power-domain-cells = <0>;117 reg = <0x10023c60 0x20>;118 #power-domain-cells = <0>;[all …]
34 #clock-cells = <0>;43 #clock-cells = <0>;50 #clock-cells = <0>;57 #size-cells = <0>;59 cpu0: cpu@0 {62 reg = <0x000>;73 performance-domains = <&performance 0>;80 reg = <0x100>;91 performance-domains = <&performance 0>;98 reg = <0x200>;[all …]
327 #size-cells = <0>;365 cpu0: cpu@0 {368 reg = <0x000>;392 reg = <0x100>;416 reg = <0x200>;440 reg = <0x300>;464 reg = <0x400>;488 reg = <0x500>;512 reg = <0x600>;536 reg = <0x700>;[all …]
293 #size-cells = <0>;327 cpu0: cpu@0 {330 reg = <0x000>;353 reg = <0x001>;376 reg = <0x002>;399 reg = <0x003>;422 reg = <0x100>;445 reg = <0x101>;468 reg = <0x102>;491 reg = <0x103>;[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0x000>;58 performance-domains = <&performance 0>;75 reg = <0x100>;77 performance-domains = <&performance 0>;94 reg = <0x200>;96 performance-domains = <&performance 0>;113 reg = <0x300>;115 performance-domains = <&performance 0>;[all …]