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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dlsi,axm5516-clks.txt18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
/openbmc/u-boot/include/configs/
H A Dls1046a_common.h38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
66 #define CONFIG_SPL_TEXT_BASE 0x10000000
67 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
68 #define CONFIG_SPL_STACK 0x10020000
69 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
70 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dmediatek-vpu.txt25 reg = <0 0x10020000 0 0x30000>,
26 <0 0x10050000 0 0x100>;
H A Dsamsung,exynos4212-fimc-is.yaml79 "^pmu@[0-9a-f]+$":
93 "^i2c-isp@[0-9a-f]+$":
115 pinctrl-0: true
146 reg = <0x12000000 0x260000>;
188 reg = <0x10020000 0x3000>;
193 reg = <0x12140000 0x100>;
196 pinctrl-0 = <&fimc_is_i2c1>;
199 #size-cells = <0>;
203 reg = <0x10>;
H A Dsamsung,fimc.yaml34 The clock specifier cell stores an index of a clock: 0, 1 for
78 "^csis@[0-9a-f]+$":
83 "^fimc@[0-9a-f]+$":
88 "^fimc-is@[0-9a-f]+$":
93 "^fimc-lite@[0-9a-f]+$":
121 ranges = <0x0 0x0 0x18000000>;
133 pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
138 reg = <0x11800000 0x1000>;
157 reg = <0x11880000 0x4000>;
165 assigned-clock-rates = <0>, <176000000>;
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h10 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS4_ADDR_BASE 0x10000000
16 #define EXYNOS4_I2C_SPACING 0x10000
18 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
19 #define EXYNOS4_PRO_ID 0x10000000
20 #define EXYNOS4_SYSREG_BASE 0x10010000
21 #define EXYNOS4_POWER_BASE 0x10020000
22 #define EXYNOS4_SWRESET 0x10020400
23 #define EXYNOS4_CLOCK_BASE 0x10030000
24 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002
15 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
16 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
17 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
18 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
19 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dingenic,aic.yaml32 const: 0
77 reg = <0x10020000 0x38>;
79 #sound-dai-cells = <0>;
88 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml67 reg = <0x10020000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dti,am65-pci-host.yaml88 reg = <0x5500000 0x1000>,
89 <0x5501000 0x1000>,
90 <0x10000000 0x2000>,
91 <0x5506000 0x1000>;
96 ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
97 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
98 ti,syscon-pcie-id = <&scm_conf 0x0210>;
99 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
100 bus-range = <0x0 0xff>;
104 msi-map = <0x0 &gic_its 0x0 0x10000>;
/openbmc/qemu/hw/arm/
H A Dvexpress.c50 #define VEXPRESS_BOARD_ID 0x8e0
54 /* Number of virtio transports to create (0..8; limited by
98 [VE_NORFLASHALIAS] = 0,
99 /* CS7: 0x10000000 .. 0x10020000 */
100 [VE_SYSREGS] = 0x10000000,
101 [VE_SP810] = 0x10001000,
102 [VE_SERIALPCI] = 0x10002000,
103 [VE_PL041] = 0x10004000,
104 [VE_MMCI] = 0x10005000,
105 [VE_KMI0] = 0x10006000,
[all …]
H A Drealview.c35 #define SMP_BOOT_ADDR 0xe0000000
36 #define SMP_BOOTREG_ADDR 0x10000030
54 0x33b,
55 0x33b,
56 0x769,
57 0x76d
68 qdev_connect_gpio_out(splitter, 0, out1); in split_irq_from_named()
70 qdev_connect_gpio_out_named(src, outname, 0, in split_irq_from_named()
71 qdev_get_gpio_in(splitter, 0)); in split_irq_from_named()
93 int is_mpcore = 0; in realview_init()
[all …]
H A Dversatilepb.c31 #define VERSATILE_FLASH_ADDR 0x34000000
68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
102 case 0: /* STATUS */ in vpb_sic_read()
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
114 return 0; in vpb_sic_read()
139 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
167 for (i = 0; i < 32; i++) { in vpb_sic_init()
172 "vpb-sic", 0x1000); in vpb_sic_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Darm,pl11x.yaml103 CLD[23:0] pads are wired up.
119 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
121 arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
147 reg = <0x10020000 0x1000>;
/openbmc/linux/arch/arm/boot/dts/intel/axm/
H A Daxm55xx.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 reg = <0x20 0x10020000 0 0x20000>;
58 #address-cells = <0>;
60 reg = <0x20 0x01001000 0 0x1000>,
61 <0x20 0x01002000 0 0x2000>,
62 <0x20 0x01004000 0 0x2000>,
63 <0x20 0x01006000 0 0x2000>;
97 reg = <0x20 0x10030000 0 0x2000>;
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts16 arm,hbi = <0x191>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 A9_0: cpu@0 {
41 reg = <0>;
69 reg = <0x60000000 0x40000000>;
77 /* Chipselect 3 is physically at 0x4c000000 */
81 reg = <0x4c000000 0x00800000>;
88 reg = <0x10020000 0x1000>;
90 interrupts = <0 44 4>;
[all …]
H A Darm-realview-eb.dtsi43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
48 vmmc: fixedregulator@0 {
57 #clock-cells = <0>;
63 #clock-cells = <0>;
71 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #clock-cells = <0>;
95 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
H A Darm-realview-pbx.dtsi44 /* 128 MiB memory @ 0x0 */
45 reg = <0x00000000 0x08000000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
102 #clock-cells = <0>;
110 #clock-cells = <0>;
118 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
31 reg = <0>;
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
168 reg = <0x0 0xc000000 0x0 0x4000000>;
169 #address-cells = <0>;
173 <&cpu0_intc 0xffffffff>,
174 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
175 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
176 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
[all …]
H A Dfu740-c000.dtsi24 #size-cells = <0>;
25 cpu0: cpu@0 {
32 reg = <0x0>;
56 reg = <0x1>;
80 reg = <0x2>;
104 reg = <0x3>;
128 reg = <0x4>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171 reg = <0x0 0xc000000 0x0 0x4000000>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dakebono.dts14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
[all …]

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