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/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/openbmc/linux/drivers/perf/hisilicon/
H A Dhisi_pcie_pmu.c24 #define HISI_PCIE_GLOBAL_CTRL 0x00
25 #define HISI_PCIE_EVENT_CTRL 0x010
26 #define HISI_PCIE_CNT 0x090
27 #define HISI_PCIE_EXT_CNT 0x110
28 #define HISI_PCIE_INT_STAT 0x150
29 #define HISI_PCIE_INT_MASK 0x154
30 #define HISI_PCIE_REG_BDF 0xfe0
31 #define HISI_PCIE_REG_VERSION 0xfe4
32 #define HISI_PCIE_REG_INFO 0xfe8
35 #define HISI_PCIE_GLOBAL_EN 0x01
[all …]
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c16 { DDRC_DBG1(0), 0x00000001 },
18 { DDRC_PWRCTL(0), 0x00000001 },
19 { DDRC_MSTR(0), 0xa3080020 },
20 { DDRC_MSTR2(0), 0x00000000 },
21 { DDRC_RFSHTMG(0), 0x006100E0 },
22 { DDRC_INIT0(0), 0xC003061B },
23 { DDRC_INIT1(0), 0x009D0000 },
24 { DDRC_INIT3(0), 0x00D4002D },
26 { DDRC_INIT4(0), 0x00330008 },
28 { DDRC_INIT4(0), 0x00310008 },
[all …]
H A Dlpddr4_timing.c15 { DDRC_DBG1(0), 0x00000001 },
16 { DDRC_PWRCTL(0), 0x00000001 },
17 { DDRC_MSTR(0), 0xa3080020 },
18 { DDRC_MSTR2(0), 0x00000000 },
19 { DDRC_RFSHTMG(0), 0x006100E0 },
20 { DDRC_INIT0(0), 0xC003061B },
21 { DDRC_INIT1(0), 0x009D0000 },
22 { DDRC_INIT3(0), 0x00D4002D },
24 { DDRC_INIT4(0), 0x00330008 },
26 { DDRC_INIT4(0), 0x00310008 },
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dperf_event_v7.c39 #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
40 #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
41 #define ARMV7_PERFCTR_ITLB_REFILL 0x02
42 #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
43 #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
44 #define ARMV7_PERFCTR_DTLB_REFILL 0x05
45 #define ARMV7_PERFCTR_MEM_READ 0x06
46 #define ARMV7_PERFCTR_MEM_WRITE 0x07
47 #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
48 #define ARMV7_PERFCTR_EXC_TAKEN 0x09
[all …]