Lines Matching +full:0 +full:x10011
39 #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
40 #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
41 #define ARMV7_PERFCTR_ITLB_REFILL 0x02
42 #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
43 #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
44 #define ARMV7_PERFCTR_DTLB_REFILL 0x05
45 #define ARMV7_PERFCTR_MEM_READ 0x06
46 #define ARMV7_PERFCTR_MEM_WRITE 0x07
47 #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
48 #define ARMV7_PERFCTR_EXC_TAKEN 0x09
49 #define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
50 #define ARMV7_PERFCTR_CID_WRITE 0x0B
59 #define ARMV7_PERFCTR_PC_WRITE 0x0C
60 #define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
61 #define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
62 #define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
63 #define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
64 #define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
65 #define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
68 #define ARMV7_PERFCTR_MEM_ACCESS 0x13
69 #define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
70 #define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
71 #define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
72 #define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
73 #define ARMV7_PERFCTR_L2_CACHE_WB 0x18
74 #define ARMV7_PERFCTR_BUS_ACCESS 0x19
75 #define ARMV7_PERFCTR_MEM_ERROR 0x1A
76 #define ARMV7_PERFCTR_INSTR_SPEC 0x1B
77 #define ARMV7_PERFCTR_TTBR_WRITE 0x1C
78 #define ARMV7_PERFCTR_BUS_CYCLES 0x1D
80 #define ARMV7_PERFCTR_CPU_CYCLES 0xFF
83 #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
84 #define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
85 #define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
86 #define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
89 #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
90 #define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
91 #define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
94 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
95 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
98 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
99 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
100 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
101 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
103 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
104 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
106 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
107 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
108 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
109 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
111 #define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
114 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
115 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
117 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
118 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
120 #define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
122 #define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
125 #define KRAIT_PMRESR0_GROUP0 0xcc
126 #define KRAIT_PMRESR1_GROUP0 0xd0
127 #define KRAIT_PMRESR2_GROUP0 0xd4
128 #define KRAIT_VPMRESR0_GROUP0 0xd8
130 #define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
131 #define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
133 #define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
134 #define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
137 #define SCORPION_LPM0_GROUP0 0x4c
138 #define SCORPION_LPM1_GROUP0 0x50
139 #define SCORPION_LPM2_GROUP0 0x54
140 #define SCORPION_L2LPM_GROUP0 0x58
141 #define SCORPION_VLPM_GROUP0 0x5c
143 #define SCORPION_ICACHE_ACCESS 0x10053
144 #define SCORPION_ICACHE_MISS 0x10052
146 #define SCORPION_DTLB_ACCESS 0x12013
147 #define SCORPION_DTLB_MISS 0x12012
149 #define SCORPION_ITLB_MISS 0x12021
535 PMU_FORMAT_ATTR(event, "config:0-7");
654 #define ARMV7_IDX_CYCLE_COUNTER 0
675 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
682 #define ARMV7_PMNC_N_MASK 0x1f
683 #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
688 #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
694 #define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */
695 #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
712 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); in armv7_pmnc_read()
720 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); in armv7_pmnc_write()
742 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); in armv7_pmnc_select_counter()
751 u32 value = 0; in armv7pmu_read_counter()
757 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); in armv7pmu_read_counter()
760 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); in armv7pmu_read_counter()
776 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value)); in armv7pmu_write_counter()
779 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value)); in armv7pmu_write_counter()
787 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); in armv7_pmnc_write_evtsel()
793 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); in armv7_pmnc_enable_counter()
799 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); in armv7_pmnc_disable_counter()
805 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); in armv7_pmnc_enable_intens()
811 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); in armv7_pmnc_disable_intens()
814 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); in armv7_pmnc_disable_intens()
823 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); in armv7_pmnc_getreset_flags()
827 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); in armv7_pmnc_getreset_flags()
840 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); in armv7_pmnc_dump_regs()
841 pr_info("PMNC =0x%08x\n", val); in armv7_pmnc_dump_regs()
843 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
844 pr_info("CNTENS=0x%08x\n", val); in armv7_pmnc_dump_regs()
846 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
847 pr_info("INTENS=0x%08x\n", val); in armv7_pmnc_dump_regs()
849 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); in armv7_pmnc_dump_regs()
850 pr_info("FLAGS =0x%08x\n", val); in armv7_pmnc_dump_regs()
852 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); in armv7_pmnc_dump_regs()
853 pr_info("SELECT=0x%08x\n", val); in armv7_pmnc_dump_regs()
855 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); in armv7_pmnc_dump_regs()
856 pr_info("CCNT =0x%08x\n", val); in armv7_pmnc_dump_regs()
861 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); in armv7_pmnc_dump_regs()
862 pr_info("CNT[%d] count =0x%08x\n", in armv7_pmnc_dump_regs()
864 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); in armv7_pmnc_dump_regs()
865 pr_info("CNT[%d] evtsel=0x%08x\n", in armv7_pmnc_dump_regs()
973 for (idx = 0; idx < cpu_pmu->num_events; ++idx) { in armv7pmu_handle_irq()
990 perf_sample_data_init(&data, 0, hwc->last_period); in armv7pmu_handle_irq()
1073 unsigned long config_base = 0; in armv7pmu_set_event_filter()
1090 return 0; in armv7pmu_set_event_filter()
1099 asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); in armv7pmu_reset()
1101 asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); in armv7pmu_reset()
1117 &armv7_a8_perf_cache_map, 0xFF); in armv7_a8_map_event()
1123 &armv7_a9_perf_cache_map, 0xFF); in armv7_a9_map_event()
1129 &armv7_a5_perf_cache_map, 0xFF); in armv7_a5_map_event()
1135 &armv7_a15_perf_cache_map, 0xFF); in armv7_a15_map_event()
1141 &armv7_a7_perf_cache_map, 0xFF); in armv7_a7_map_event()
1147 &armv7_a12_perf_cache_map, 0xFF); in armv7_a12_map_event()
1153 &krait_perf_cache_map, 0xFFFFF); in krait_map_event()
1159 &krait_perf_cache_map, 0xFFFFF); in krait_map_event_no_branch()
1165 &scorpion_perf_cache_map, 0xFFFFF); in scorpion_map_event()
1289 * 31 30 24 16 8 0
1291 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0
1299 * EN | G=3 | G=2 | G=1 | G=0
1303 * hwc->config_base = 0xNRCCG
1310 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
1324 #define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */
1325 #define EVENT_GROUP(event) ((event) & 0xf) /* G */
1326 #define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */
1335 case 0: in krait_read_pmresrn()
1336 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); in krait_read_pmresrn()
1339 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); in krait_read_pmresrn()
1342 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); in krait_read_pmresrn()
1354 case 0: in krait_write_pmresrn()
1355 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); in krait_write_pmresrn()
1358 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); in krait_write_pmresrn()
1361 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); in krait_write_pmresrn()
1371 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); in venum_read_pmresr()
1377 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); in venum_write_pmresr()
1427 mask = 0xff << group_shift; in krait_evt_setup()
1462 mask = 0xff << group_shift; in clear_pmresrn_group()
1469 return 0; in clear_pmresrn_group()
1564 krait_write_pmresrn(0, 0); in krait_pmu_reset()
1565 krait_write_pmresrn(1, 0); in krait_pmu_reset()
1566 krait_write_pmresrn(2, 0); in krait_pmu_reset()
1569 venum_write_pmresr(0); in krait_pmu_reset()
1575 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); in krait_pmu_reset()
1591 bit -= krait_get_pmresrn_event(0); in krait_event_to_bit()
1622 if (venum_event && (code & 0xe0)) in krait_pmu_get_event_idx()
1631 if (idx < 0 && bit >= 0) in krait_pmu_get_event_idx()
1676 * 31 30 24 16 8 0
1678 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0
1688 * EN | G=3 | G=2 | G=1 | G=0
1693 * hwc->config_base = 0xNRCCG
1700 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2
1714 case 0: in scorpion_read_pmresrn()
1715 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); in scorpion_read_pmresrn()
1718 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); in scorpion_read_pmresrn()
1721 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); in scorpion_read_pmresrn()
1724 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); in scorpion_read_pmresrn()
1736 case 0: in scorpion_write_pmresrn()
1737 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); in scorpion_write_pmresrn()
1740 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); in scorpion_write_pmresrn()
1743 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); in scorpion_write_pmresrn()
1746 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); in scorpion_write_pmresrn()
1774 mask = 0xff << group_shift; in scorpion_evt_setup()
1786 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); in scorpion_evt_setup()
1897 scorpion_write_pmresrn(0, 0); in scorpion_pmu_reset()
1898 scorpion_write_pmresrn(1, 0); in scorpion_pmu_reset()
1899 scorpion_write_pmresrn(2, 0); in scorpion_pmu_reset()
1900 scorpion_write_pmresrn(3, 0); in scorpion_pmu_reset()
1903 venum_write_pmresr(0); in scorpion_pmu_reset()
1909 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); in scorpion_pmu_reset()
1924 bit -= scorpion_get_pmresrn_event(0); in scorpion_event_to_bit()
1961 if (idx < 0 && bit >= 0) in scorpion_pmu_get_event_idx()