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/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,pericfg.yaml59 reg = <0x10003000 0x1000>;
67 reg = <0x10003000 0x1000>;
H A Dmediatek,mt7986-wed-pcie.yaml41 reg = <0 0x10003000 0 0x10>;
H A Dmediatek,mt8192-sys-clock.yaml45 reg = <0x10000000 0x1000>;
52 reg = <0x10001000 0x1000>;
59 reg = <0x10003000 0x1000>;
66 reg = <0x1000c000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml54 const: 0
63 minimum: 0
71 minimum: 0
92 reg = <0x10003000 0x40>;
105 reg = <0x10003000 0x4c>;
113 #clock-cells = <0>;
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dfsl,imxgpt.yaml73 reg = <0x10003000 0x1000>;
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dinterrupts.txt17 interrupts = <5 0>, <6 0>;
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
55 reg = <0x10140000 0x1000>;
62 reg = <0x10003000 0x1000>;
72 - bits[3:0] trigger type and level flags
83 reg = <0x41>;
99 reg = <0x2b>;
102 interrupts = <3 0x8>;
105 #size-cells = <0>;
107 threshold = <0x40>;
/openbmc/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsc9836.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0 0x0>;
29 reg = <0x0 0x1>;
36 reg = <0x0 0x2>;
43 reg = <0x0 0x3>;
50 reg = <0 0x10003000 0 0x1000>;
64 reg = <0 0x10001000 0 0x1000>;
78 #size-cells = <0>;
80 port@0 {
[all …]
/openbmc/qemu/hw/arm/
H A Dversatilepb.c31 #define VERSATILE_FLASH_ADDR 0x34000000
68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
102 case 0: /* STATUS */ in vpb_sic_read()
113 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); in vpb_sic_read()
114 return 0; in vpb_sic_read()
139 s->pic_enable |= (value & 0x7fe00000); in vpb_sic_write()
147 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); in vpb_sic_write()
167 for (i = 0; i < 32; i++) { in vpb_sic_init()
172 "vpb-sic", 0x1000); in vpb_sic_init()
[all …]
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm6318.dtsi21 reg = <0x10000000 0x4>;
23 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
61 reg = <0x10000008 0x4>;
74 reg = <0x10000010 0x4>;
80 reg = <0x10000068 0xc>;
[all …]
H A Dbrcm,bcm6328.dtsi21 reg = <0x10000000 0x4>;
23 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
49 #clock-cells = <0>;
55 #clock-cells = <0>;
62 reg = <0x10000004 0x4>;
75 reg = <0x10000010 0x4>;
81 reg = <0x10000068 0x4>;
87 offset = <0x0>;
[all …]
H A Dbrcm,bcm6362.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
76 reg = <0x10000008 0x4>;
82 offset = <0x0>;
83 mask = <0x1>;
[all …]
H A Dbrcm,bcm63268.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
69 reg = <0x100000ac 0x4>;
82 reg = <0x10000008 0x4>;
88 offset = <0x0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dmediatek,mt76.yaml136 "^r[0-9]+":
157 "^b[0-9]+$":
227 wifi@0,0 {
229 reg = <0x0000 0 0 0 0>;
231 mediatek,mtd-eeprom = <&factory 0x8000>;
266 reg = <0x10300000 0x100000>;
280 reg = <0x10300000 0x100000>;
293 reg = <0x18000000 0x1000000>,
294 <0x10003000 0x1000>,
295 <0x11d10000 0x1000>;
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
40 reg = <0x1>;
50 reg = <0x2>;
60 reg = <0x3>;
71 #clock-cells = <0>;
76 #clock-cells = <0>;
81 clk26m: oscillator-0 {
83 #clock-cells = <0>;
[all …]
H A Dtegra186.dtsi19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
36 reg = <0x0 0x02490000 0x0 0x10000>;
56 reg = <0x0 0x03100000 0x0 0x10000>;
63 reg = <0x0 0x3160000 0x0 0x100>;
66 #size-cells = <0>;
76 reg = <0x0 0x3180000 0x0 0x100>;
79 #size-cells = <0>;
89 reg = <0x0 0x3190000 0x0 0x100>;
92 #size-cells = <0>;
[all …]
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4770.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x40>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
58 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
H A Dx1830.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
18 reg = <0>;
26 #address-cells = <0>;
34 reg = <0x10001000 0x50>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
56 reg = <0x10000000 0x100>;
59 ranges = <0x0 0x10000000 0x100>;
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx27.c15 #define MX27_CCM_BASE_ADDR 0x10027000
16 #define MX27_GPT1_BASE_ADDR 0x10003000
22 #define CCM_CSCR (ccm + 0x00)
23 #define CCM_MPCTL0 (ccm + 0x04)
24 #define CCM_MPCTL1 (ccm + 0x08)
25 #define CCM_SPCTL0 (ccm + 0x0c)
26 #define CCM_SPCTL1 (ccm + 0x10)
27 #define CCM_PCDR0 (ccm + 0x18)
28 #define CCM_PCDR1 (ccm + 0x1c)
29 #define CCM_PCCR0 (ccm + 0x20)
[all …]

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