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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dbrcm,bcm6345-reset.yaml35 reg = <0x10000010 0x4>;
/openbmc/u-boot/arch/mips/dts/
H A Dbrcm,bcm6318.dtsi21 reg = <0x10000000 0x4>;
23 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
61 reg = <0x10000008 0x4>;
74 reg = <0x10000010 0x4>;
80 reg = <0x10000068 0xc>;
[all …]
H A Dbrcm,bcm6368.dtsi20 reg = <0x10000000 0x4>;
22 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
48 #clock-cells = <0>;
55 reg = <0x10000004 0x4>;
62 reg = <0x18000000 0x2000000>;
78 reg = <0x10000008 0x4>;
84 offset = <0x0>;
85 mask = <0x1>;
[all …]
H A Dbrcm,bcm6328.dtsi21 reg = <0x10000000 0x4>;
23 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
49 #clock-cells = <0>;
55 #clock-cells = <0>;
62 reg = <0x10000004 0x4>;
75 reg = <0x10000010 0x4>;
81 reg = <0x10000068 0x4>;
87 offset = <0x0>;
[all …]
H A Dbrcm,bcm6362.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
76 reg = <0x10000008 0x4>;
82 offset = <0x0>;
83 mask = <0x1>;
[all …]
H A Dbrcm,bcm63268.dtsi22 reg = <0x10000000 0x4>;
24 #size-cells = <0>;
27 cpu@0 {
30 reg = <0>;
50 #clock-cells = <0>;
56 #clock-cells = <0>;
63 reg = <0x10000004 0x4>;
69 reg = <0x100000ac 0x4>;
82 reg = <0x10000008 0x4>;
88 offset = <0x0>;
[all …]
/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm6362.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
H A Dbcm6368.dtsi13 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
33 #clock-cells = <0>;
48 #address-cells = <0>;
64 reg = <0x10000004 0x4>;
70 reg = <0x10000008 0x4>;
75 offset = <0x0>;
76 mask = <0x1>;
82 reg = <0x10000010 0x4>;
[all …]
H A Dbcm6328.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
41 #clock-cells = <0>;
55 #address-cells = <0>;
71 reg = <0x10000004 0x4>;
77 reg = <0x10000010 0x4>;
83 reg = <0x10000020 0x10>,
84 <0x10000030 0x10>;
[all …]
H A Dbcm63268.dtsi14 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
34 #clock-cells = <0>;
42 #clock-cells = <0>;
58 #address-cells = <0>;
74 reg = <0x10000004 0x4>;
80 reg = <0x10000008 0x4>;
85 offset = <0x0>;
86 mask = <0x1>;
[all …]
/openbmc/u-boot/cmd/aspeed/
H A Ddptest.h8 #define SYS_REST 0x1e6e2040
9 #define SYS_REST_CLR 0x1e6e2044
12 #define DP_TX_INT_CLEAR 0x1e6eb040
13 #define DP_TX_INT_STATUS 0x1e6eb044
15 #define DP_TX_IRQ_CFG 0x1e6eb080
16 #define DP_TX_EVENT_CFG 0x1e6eb084
18 #define DP_AUX_REQ_CFG 0x1e6eb088
19 #define DP_AUX_ADDR_LEN 0x1e6eb08c
20 #define DP_AUX_STATUS 0x1e6eb0b0
22 #define DP_AUX_W_D_0 0x1e6eb090
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgk104.c44 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000800, 0x00000800); in gk104_chan_stop()
52 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400); in gk104_chan_start()
60 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x00000000); in gk104_chan_unbind()
68 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x80000000 | chan->inst->addr >> 12); in gk104_chan_bind_inst()
77 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x000f0000, runl->id << 16); in gk104_chan_bind()
88 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd)); in gk104_chan_ramfc_write()
89 nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd)); in gk104_chan_ramfc_write()
90 nvkm_wo32(chan->inst, 0x10, 0x0000face); in gk104_chan_ramfc_write()
91 nvkm_wo32(chan->inst, 0x30, 0xfffff902); in gk104_chan_ramfc_write()
92 nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset)); in gk104_chan_ramfc_write()
[all …]
H A Dgf100.c43 nvkm_wr32(chan->cgrp->runl->fifo->engine.subdev.device, 0x002634, chan->id); in gf100_chan_preempt()
51 nvkm_mask(device, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000); in gf100_chan_stop()
59 nvkm_wr32(device, 0x003004 + (chan->id * 8), 0x001f0001); in gf100_chan_start()
73 nvkm_wr32(device, 0x003000 + (chan->id * 8), 0x00000000); in gf100_chan_unbind()
81 nvkm_wr32(device, 0x003000 + (chan->id * 8), 0xc0000000 | chan->inst->addr >> 12); in gf100_chan_bind()
91 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd)); in gf100_chan_ramfc_write()
92 nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd)); in gf100_chan_ramfc_write()
93 nvkm_wo32(chan->inst, 0x10, 0x0000face); in gf100_chan_ramfc_write()
94 nvkm_wo32(chan->inst, 0x30, 0xfffff902); in gf100_chan_ramfc_write()
95 nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset)); in gf100_chan_ramfc_write()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml102 between 0 and infinite time, until a wake-up event occurs.
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
167 0| 1 time(ms)
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
380 #size-cells = <0>;
383 cpu@0 {
386 reg = <0x0 0x0>;
395 reg = <0x0 0x1>;
404 reg = <0x0 0x100>;
413 reg = <0x0 0x101>;
[all …]
/openbmc/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]