Lines Matching +full:0 +full:x10000010
44 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000800, 0x00000800); in gk104_chan_stop()
52 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x00000400, 0x00000400); in gk104_chan_start()
60 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x00000000); in gk104_chan_unbind()
68 nvkm_wr32(device, 0x800000 + (chan->id * 8), 0x80000000 | chan->inst->addr >> 12); in gk104_chan_bind_inst()
77 nvkm_mask(device, 0x800004 + (chan->id * 8), 0x000f0000, runl->id << 16); in gk104_chan_bind()
88 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd)); in gk104_chan_ramfc_write()
89 nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd)); in gk104_chan_ramfc_write()
90 nvkm_wo32(chan->inst, 0x10, 0x0000face); in gk104_chan_ramfc_write()
91 nvkm_wo32(chan->inst, 0x30, 0xfffff902); in gk104_chan_ramfc_write()
92 nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset)); in gk104_chan_ramfc_write()
93 nvkm_wo32(chan->inst, 0x4c, upper_32_bits(offset) | (limit2 << 16)); in gk104_chan_ramfc_write()
94 nvkm_wo32(chan->inst, 0x84, 0x20400000); in gk104_chan_ramfc_write()
95 nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm); in gk104_chan_ramfc_write()
96 nvkm_wo32(chan->inst, 0x9c, 0x00000100); in gk104_chan_ramfc_write()
97 nvkm_wo32(chan->inst, 0xac, 0x0000001f); in gk104_chan_ramfc_write()
98 nvkm_wo32(chan->inst, 0xe4, priv ? 0x00000020 : 0x00000000); in gk104_chan_ramfc_write()
99 nvkm_wo32(chan->inst, 0xe8, chan->id); in gk104_chan_ramfc_write()
100 nvkm_wo32(chan->inst, 0xb8, 0xf8000000); in gk104_chan_ramfc_write()
101 nvkm_wo32(chan->inst, 0xf8, 0x10003080); /* 0x002310 */ in gk104_chan_ramfc_write()
102 nvkm_wo32(chan->inst, 0xfc, 0x10000010); /* 0x002350 */ in gk104_chan_ramfc_write()
104 return 0; in gk104_chan_ramfc_write()
110 .devm = 0xfff,
117 .size = 0x200,
136 u32 ptr0, ptr1 = 0; in gk104_ectx_bind()
137 u64 addr = 0ULL; in gk104_ectx_bind()
141 case NVKM_ENGINE_GR : ptr0 = 0x0210; break; in gk104_ectx_bind()
142 case NVKM_ENGINE_SEC : ptr0 = 0x0220; break; in gk104_ectx_bind()
143 case NVKM_ENGINE_MSPDEC: ptr0 = 0x0250; break; in gk104_ectx_bind()
144 case NVKM_ENGINE_MSPPP : ptr0 = 0x0260; break; in gk104_ectx_bind()
145 case NVKM_ENGINE_MSVLD : ptr0 = 0x0270; break; in gk104_ectx_bind()
146 case NVKM_ENGINE_VIC : ptr0 = 0x0280; break; in gk104_ectx_bind()
147 case NVKM_ENGINE_MSENC : ptr0 = 0x0290; break; in gk104_ectx_bind()
149 ptr1 = 0x0270; in gk104_ectx_bind()
150 ptr0 = 0x0210; in gk104_ectx_bind()
154 ptr1 = 0x0290; in gk104_ectx_bind()
155 ptr0 = 0x0210; in gk104_ectx_bind()
168 nvkm_wo32(chan->inst, ptr0 + 0, lower_32_bits(addr)); in gk104_ectx_bind()
171 nvkm_wo32(chan->inst, ptr1 + 0, lower_32_bits(addr)); in gk104_ectx_bind()
187 return nvkm_memory_map(vctx->inst, 0, vctx->vmm, vctx->vma, &args, sizeof(args)); in gk104_ectx_ctor()
206 u32 stat = nvkm_rd32(engn->runl->fifo->engine.subdev.device, 0x002640 + (engn->id * 0x08)); in gk104_engn_status()
208 status->busy = !!(stat & 0x80000000); in gk104_engn_status()
209 status->faulted = !!(stat & 0x40000000); in gk104_engn_status()
210 status->next.tsg = !!(stat & 0x10000000); in gk104_engn_status()
211 status->next.id = (stat & 0x0fff0000) >> 16; in gk104_engn_status()
212 status->chsw = !!(stat & 0x00008000); in gk104_engn_status()
213 status->save = !!(stat & 0x00004000); in gk104_engn_status()
214 status->load = !!(stat & 0x00002000); in gk104_engn_status()
215 status->prev.tsg = !!(stat & 0x00001000); in gk104_engn_status()
216 status->prev.id = (stat & 0x00000fff); in gk104_engn_status()
293 return !(nvkm_rd32(device, 0x003080 + (runq->id * 4)) & 0x0000e000); in gk104_runq_idle()
298 { 0x00000001, "HCE_RE_ILLEGAL_OP" },
299 { 0x00000002, "HCE_RE_ALIGNB" },
300 { 0x00000004, "HCE_PRIV" },
301 { 0x00000008, "HCE_ILLEGAL_MTHD" },
302 { 0x00000010, "HCE_ILLEGAL_CLASS" },
311 u32 mask = nvkm_rd32(device, 0x04014c + (runq->id * 0x2000)); in gk104_runq_intr_1()
312 u32 stat = nvkm_rd32(device, 0x040148 + (runq->id * 0x2000)) & mask; in gk104_runq_intr_1()
313 u32 chid = nvkm_rd32(device, 0x040120 + (runq->id * 0x2000)) & 0xfff; in gk104_runq_intr_1()
316 if (stat & 0x80000000) { in gk104_runq_intr_1()
319 stat &= ~0x80000000; in gk104_runq_intr_1()
326 nvkm_rd32(device, 0x040150 + (runq->id * 0x2000)), in gk104_runq_intr_1()
327 nvkm_rd32(device, 0x040154 + (runq->id * 0x2000))); in gk104_runq_intr_1()
330 nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), stat); in gk104_runq_intr_1()
336 { 0x00000001, "MEMREQ" },
337 { 0x00000002, "MEMACK_TIMEOUT" },
338 { 0x00000004, "MEMACK_EXTRA" },
339 { 0x00000008, "MEMDAT_TIMEOUT" },
340 { 0x00000010, "MEMDAT_EXTRA" },
341 { 0x00000020, "MEMFLUSH" },
342 { 0x00000040, "MEMOP" },
343 { 0x00000080, "LBCONNECT" },
344 { 0x00000100, "LBREQ" },
345 { 0x00000200, "LBACK_TIMEOUT" },
346 { 0x00000400, "LBACK_EXTRA" },
347 { 0x00000800, "LBDAT_TIMEOUT" },
348 { 0x00001000, "LBDAT_EXTRA" },
349 { 0x00002000, "GPFIFO" },
350 { 0x00004000, "GPPTR" },
351 { 0x00008000, "GPENTRY" },
352 { 0x00010000, "GPCRC" },
353 { 0x00020000, "PBPTR" },
354 { 0x00040000, "PBENTRY" },
355 { 0x00080000, "PBCRC" },
356 { 0x00100000, "XBARCONNECT" },
357 { 0x00200000, "METHOD" },
358 { 0x00400000, "METHODCRC" },
359 { 0x00800000, "DEVICE" },
360 { 0x02000000, "SEMAPHORE" },
361 { 0x04000000, "ACQUIRE" },
362 { 0x08000000, "PRI" },
363 { 0x20000000, "NO_CTXSW_SEG" },
364 { 0x40000000, "PBSEG" },
365 { 0x80000000, "SIGNATURE" },
385 nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), 0xffffffff); /* HCE.INTR */ in gk104_runq_init()
386 nvkm_wr32(device, 0x04014c + (runq->id * 0x2000), 0xffffffff); /* HCE.INTREN */ in gk104_runq_init()
392 return nvkm_rd32(runq->fifo->engine.subdev.device, 0x002390 + (runq->id * 0x04)); in gk104_runq_runm()
406 nvkm_wr32(runl->fifo->engine.subdev.device, 0x00262c, BIT(runl->id)); in gk104_runl_fault_clear()
412 nvkm_mask(runl->fifo->engine.subdev.device, 0x002630, BIT(runl->id), 0x00000000); in gk104_runl_allow()
418 nvkm_mask(runl->fifo->engine.subdev.device, 0x002630, BIT(runl->id), BIT(runl->id)); in gk104_runl_block()
426 return nvkm_rd32(device, 0x002284 + (runl->id * 0x08)) & 0x00100000; in gk104_runl_pending()
438 case NVKM_MEM_TARGET_VRAM: target = 0; break; in gk104_runl_commit()
446 nvkm_wr32(device, 0x002270, (target << 28) | (addr >> 12)); in gk104_runl_commit()
447 nvkm_wr32(device, 0x002274, (runl->id << 20) | count); in gk104_runl_commit()
454 nvkm_wo32(memory, offset + 0, chan->id); in gk104_runl_insert_chan()
455 nvkm_wo32(memory, offset + 4, 0x00000000); in gk104_runl_insert_chan()
474 { 0x00, "GR", NULL, NVKM_ENGINE_GR },
475 { 0x01, "DISPLAY" },
476 { 0x02, "CAPTURE" },
477 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
478 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
479 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
480 { 0x06, "SCHED" },
481 { 0x07, "HOST0" },
482 { 0x08, "HOST1" },
483 { 0x09, "HOST2" },
484 { 0x0a, "HOST3" },
485 { 0x0b, "HOST4" },
486 { 0x0c, "HOST5" },
487 { 0x0d, "HOST6" },
488 { 0x0e, "HOST7" },
489 { 0x0f, "HOSTSR" },
490 { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
491 { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
492 { 0x13, "PERF" },
493 { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC },
494 { 0x15, "CE0", NULL, NVKM_ENGINE_CE, 0 },
495 { 0x16, "CE1", NULL, NVKM_ENGINE_CE, 1 },
496 { 0x17, "PMU" },
497 { 0x18, "PTP" },
498 { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
499 { 0x1b, "CE2", NULL, NVKM_ENGINE_CE, 2 },
505 { 0x00, "PDE" },
506 { 0x01, "PDE_SIZE" },
507 { 0x02, "PTE" },
508 { 0x03, "VA_LIMIT_VIOLATION" },
509 { 0x04, "UNBOUND_INST_BLOCK" },
510 { 0x05, "PRIV_VIOLATION" },
511 { 0x06, "RO_VIOLATION" },
512 { 0x07, "WO_VIOLATION" },
513 { 0x08, "PITCH_MASK_VIOLATION" },
514 { 0x09, "WORK_CREATION" },
515 { 0x0a, "UNSUPPORTED_APERTURE" },
516 { 0x0b, "COMPRESSION_FAILURE" },
517 { 0x0c, "UNSUPPORTED_KIND" },
518 { 0x0d, "REGION_VIOLATION" },
519 { 0x0e, "BOTH_PTES_VALID" },
520 { 0x0f, "INFO_TYPE_POISONED" },
526 { 0x00, "VIP" },
527 { 0x01, "CE0" },
528 { 0x02, "CE1" },
529 { 0x03, "DNISO" },
530 { 0x04, "FE" },
531 { 0x05, "FECS" },
532 { 0x06, "HOST" },
533 { 0x07, "HOST_CPU" },
534 { 0x08, "HOST_CPU_NB" },
535 { 0x09, "ISO" },
536 { 0x0a, "MMU" },
537 { 0x0b, "MSPDEC" },
538 { 0x0c, "MSPPP" },
539 { 0x0d, "MSVLD" },
540 { 0x0e, "NISO" },
541 { 0x0f, "P2P" },
542 { 0x10, "PD" },
543 { 0x11, "PERF" },
544 { 0x12, "PMU" },
545 { 0x13, "RASTERTWOD" },
546 { 0x14, "SCC" },
547 { 0x15, "SCC_NB" },
548 { 0x16, "SEC" },
549 { 0x17, "SSYNC" },
550 { 0x18, "GR_CE" },
551 { 0x19, "CE2" },
552 { 0x1a, "XV" },
553 { 0x1b, "MMU_NB" },
554 { 0x1c, "MSENC" },
555 { 0x1d, "DFALCON" },
556 { 0x1e, "SKED" },
557 { 0x1f, "AFALCON" },
563 { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
564 { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
565 { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
566 { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
567 { 0x0c, "RAST" },
568 { 0x0d, "GCC" },
569 { 0x0e, "GPCCS" },
570 { 0x0f, "PROP_0" },
571 { 0x10, "PROP_1" },
572 { 0x11, "PROP_2" },
573 { 0x12, "PROP_3" },
574 { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
575 { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
576 { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
577 { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
578 { 0x1f, "GPM" },
579 { 0x20, "LTP_UTLB_0" },
580 { 0x21, "LTP_UTLB_1" },
581 { 0x22, "LTP_UTLB_2" },
582 { 0x23, "LTP_UTLB_3" },
583 { 0x24, "GPC_RGG_UTLB" },
599 { 0x01, "BIND_NOT_UNBOUND" },
600 { 0x02, "SNOOP_WITHOUT_BAR1" },
601 { 0x03, "UNBIND_WHILE_RUNNING" },
602 { 0x05, "INVALID_RUNLIST" },
603 { 0x06, "INVALID_CTX_TGT" },
604 { 0x0b, "UNBIND_WHILE_PARKED" },
612 u32 intr = nvkm_rd32(subdev->device, 0x00252c); in gk104_fifo_intr_bind()
613 u32 code = intr & 0x000000ff; in gk104_fifo_intr_bind()
624 u32 stat = nvkm_rd32(device, 0x00256c); in gk104_fifo_intr_chsw()
627 nvkm_wr32(device, 0x00256c, stat); in gk104_fifo_intr_chsw()
634 u32 stat = nvkm_rd32(subdev->device, 0x00259c); in gk104_fifo_intr_dropped_fault()
644 u32 mask = nvkm_rd32(device, 0x002a00); in gk104_fifo_intr_runlist()
647 nvkm_wr32(device, 0x002a00, BIT(runl->id)); in gk104_fifo_intr_runlist()
657 u32 mask = nvkm_rd32(device, 0x002140); in gk104_fifo_intr()
658 u32 stat = nvkm_rd32(device, 0x002100) & mask; in gk104_fifo_intr()
660 if (stat & 0x00000001) { in gk104_fifo_intr()
662 nvkm_wr32(device, 0x002100, 0x00000001); in gk104_fifo_intr()
663 stat &= ~0x00000001; in gk104_fifo_intr()
666 if (stat & 0x00000010) { in gk104_fifo_intr()
668 nvkm_wr32(device, 0x002100, 0x00000010); in gk104_fifo_intr()
669 stat &= ~0x00000010; in gk104_fifo_intr()
672 if (stat & 0x00000100) { in gk104_fifo_intr()
674 nvkm_wr32(device, 0x002100, 0x00000100); in gk104_fifo_intr()
675 stat &= ~0x00000100; in gk104_fifo_intr()
678 if (stat & 0x00010000) { in gk104_fifo_intr()
680 nvkm_wr32(device, 0x002100, 0x00010000); in gk104_fifo_intr()
681 stat &= ~0x00010000; in gk104_fifo_intr()
684 if (stat & 0x00800000) { in gk104_fifo_intr()
686 nvkm_wr32(device, 0x002100, 0x00800000); in gk104_fifo_intr()
687 stat &= ~0x00800000; in gk104_fifo_intr()
690 if (stat & 0x01000000) { in gk104_fifo_intr()
692 nvkm_wr32(device, 0x002100, 0x01000000); in gk104_fifo_intr()
693 stat &= ~0x01000000; in gk104_fifo_intr()
696 if (stat & 0x08000000) { in gk104_fifo_intr()
698 nvkm_wr32(device, 0x002100, 0x08000000); in gk104_fifo_intr()
699 stat &= ~0x08000000; in gk104_fifo_intr()
702 if (stat & 0x10000000) { in gk104_fifo_intr()
704 stat &= ~0x10000000; in gk104_fifo_intr()
707 if (stat & 0x20000000) { in gk104_fifo_intr()
709 stat &= ~0x20000000; in gk104_fifo_intr()
712 if (stat & 0x40000000) { in gk104_fifo_intr()
714 stat &= ~0x40000000; in gk104_fifo_intr()
717 if (stat & 0x80000000) { in gk104_fifo_intr()
718 nvkm_wr32(device, 0x002100, 0x80000000); in gk104_fifo_intr()
719 nvkm_event_ntfy(&fifo->nonstall.event, 0, NVKM_FIFO_NONSTALL_EVENT); in gk104_fifo_intr()
720 stat &= ~0x80000000; in gk104_fifo_intr()
726 nvkm_mask(device, 0x002140, stat, 0x00000000); in gk104_fifo_intr()
728 nvkm_wr32(device, 0x002100, stat); in gk104_fifo_intr()
739 nvkm_wr32(device, 0x000204, mask); in gk104_fifo_init_pbdmas()
740 nvkm_mask(device, 0x002a04, 0xbfffffff, 0xbfffffff); in gk104_fifo_init_pbdmas()
749 nvkm_wr32(device, 0x002254, 0x10000000 | fifo->userd.bar1->addr >> 12); in gk104_fifo_init()
751 nvkm_wr32(device, 0x002100, 0xffffffff); in gk104_fifo_init()
752 nvkm_wr32(device, 0x002140, 0x7fffffff); in gk104_fifo_init()
764 nvkm_list_foreach(tdev, &device->top->device, head, tdev->runlist >= 0) { in gk104_fifo_runl_ctor()
767 runl = nvkm_runl_new(fifo, tdev->runlist, tdev->runlist, 0); in gk104_fifo_runl_ctor()
780 if (tdev->engine < 0) in gk104_fifo_runl_ctor()
788 nvkm_runl_add(runl, 15, &gf100_engn_sw, NVKM_ENGINE_SW, 0); in gk104_fifo_runl_ctor()
798 return 0; in gk104_fifo_runl_ctor()
825 .chan = {{ 0, 0, KEPLER_CHANNEL_GPFIFO_A }, &gk104_chan },