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/openbmc/linux/arch/arm/mach-imx/
H A Dhardware.h21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
41 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
43 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
44 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
45 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
47 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
48 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
51 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
[all …]
/openbmc/qemu/tests/multiboot/
H A Daout_kludge.S25 #define MB_MAGIC 0x1badb002
26 #define MB_FLAGS 0x10000
34 #define LAST_BYTE_VALUE 0xa5
47 .int 0x100000
48 .int 0x100000
54 .int 0x100000
55 .int 0x100000
57 .int 0
61 .int 0x100000
62 .int 0x100000
[all …]
H A Dmmap.out10 0x0 - 0x9fc00: type 1 [entry size: 20]
11 0x9fc00 - 0xa0000: type 2 [entry size: 20]
12 0xf0000 - 0x100000: type 2 [entry size: 20]
13 0x100000 - 0x7fe0000: type 1 [entry size: 20]
14 0x7fe0000 - 0x8000000: type 2 [entry size: 20]
15 0xfffc0000 - 0x100000000: type 2 [entry size: 20]
17 mmap start: 0x9000
18 mmap end: 0x9090
19 real mmap end: 0x9090
28 0x0 - 0x9fc00: type 1 [entry size: 20]
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dfixed-partitions.yaml33 "@[0-9a-f]+$":
59 partition@0 {
61 reg = <0x0000000 0x100000>;
66 reg = <0x0100000 0x200000>;
77 partition@0 {
79 reg = <0x00000000 0x1 0x00000000>;
91 partition@0 {
93 reg = <0x0 0x00000000 0x2 0x00000000>;
99 reg = <0x2 0x00000000 0x1 0x00000000>;
109 partition@0 {
[all …]
H A Dbrcm,bcm4908-partitions.yaml33 "^partition@[0-9a-f]+$":
53 partition@0 {
55 reg = <0x0 0x100000>;
60 reg = <0x100000 0xf00000>;
65 reg = <0x1000000 0xf00000>;
70 reg = <0x1f00000 0x100000>;
H A Dlinksys,ns-partitions.yaml34 "^partition@[0-9a-f]+$":
56 partition@0 {
58 reg = <0x0 0x100000>;
64 reg = <0x100000 0x100000>;
69 reg = <0x200000 0xf00000>;
74 reg = <0x1100000 0xf00000>;
/openbmc/qemu/tests/qemu-iotests/
H A D131.out22 read 524288/524288 bytes at offset 0
31 wrote 2097152/2097152 bytes at offset 0
34 0 0x200000 TEST_DIR/t.IMGFMT
35 discard 1048576/1048576 bytes at offset 0
38 0x100000 0x100000 TEST_DIR/t.IMGFMT
39 read 1048576/1048576 bytes at offset 0
45 0x100000 0x100000 TEST_DIR/t.IMGFMT
46 0x200000 0x100000 TEST_DIR/t.IMGFMT
58 0 0x100000 TEST_DIR/t.IMGFMT
59 0x100000 0x100000 TEST_DIR/t.IMGFMT
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/openbmc/u-boot/include/configs/
H A Dls1088aqds.h18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_ENV_SIZE 0x20000
21 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
28 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #define CONFIG_SYS_MMC_ENV_DEV 0
32 #define CONFIG_ENV_SIZE 0x2000
34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
35 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dimx6_spl.h12 * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
14 * - BOOT ROM stack is at 0x0091FFB8
16 * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
17 * fit between 0x00907000 and 0x00918000.
20 * and some padding thus 'our' max size is really 0x00908000 - 0x00918000
23 #define CONFIG_SPL_TEXT_BASE 0x00908000
24 #define CONFIG_SPL_MAX_SIZE 0x10000
25 #define CONFIG_SPL_STACK 0x0091FFB8
31 #define CONFIG_SPL_PAD_TO 0x11000
41 #define CONFIG_SPL_SATA_BOOT_DEVICE 0
[all …]
H A Dls1046a_common.h38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
66 #define CONFIG_SPL_TEXT_BASE 0x10000000
67 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
68 #define CONFIG_SPL_STACK 0x10020000
69 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
70 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
71 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
[all …]
H A Dls1043a_common.h38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
67 #define CONFIG_SPL_TEXT_BASE 0x10000000
68 #define CONFIG_SPL_MAX_SIZE 0x17000
69 #define CONFIG_SPL_STACK 0x1001e000
70 #define CONFIG_SPL_PAD_TO 0x1d000
74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
75 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c56 writel((mem.control1 | (0 << mem.dll_resync)), in phy_control_reset()
59 writel((mem.control0 | (0 << mem.dll_on)), in phy_control_reset()
69 unsigned long mask = 0; in dmc_config_mrs()
74 for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { in dmc_config_mrs()
95 sdelay(0x100000); in dmc_init()
102 phy_control_reset(0, dmc); in dmc_init()
140 sdelay(0x100000); in dmc_init()
143 dmc_config_mrs(dmc, 0); in dmc_init()
144 sdelay(0x100000); in dmc_init()
148 sdelay(0x100000); in dmc_init()
[all …]
/openbmc/linux/Documentation/arch/arm/sa1100/
H A Dassabet.rst91 load zImage -r -b 0x100000
95 load -m ymodem -r -b 0x100000
99 fis create "Linux kernel" -b 0x100000 -l 0xc0000
108 load ramdisk_image.gz -r -b 0x800000
119 exec -b 0x100000 -l 0xc0000
140 load sample_img.jffs2 -r -b 0x100000
144 RedBoot> load sample_img.jffs2 -r -b 0x100000
145 Raw file loaded 0x00100000-0x00377424
154 0x500E0000 .. 0x503C0000
162 size of unallocated flash: 0x503c0000 - 0x500e0000 = 0x2e0000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
H A Dp1022ds_32b.dts45 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
46 0x1 0x0 0x0 0xe0000000 0x08000000
47 0x2 0x0 0x0 0xff800000 0x00040000
48 0x3 0x0 0x0 0xffdf0000 0x00008000>;
49 reg = <0x0 0xffe05000 0 0x1000>;
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0x0 0xffe09000 0 0x1000>;
60 pcie@0 {
[all …]
H A Dp1022ds_36b.dts45 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
46 0x1 0x0 0xf 0xe0000000 0x08000000
47 0x2 0x0 0xf 0xff800000 0x00040000
48 0x3 0x0 0xf 0xffdf0000 0x00008000>;
49 reg = <0xf 0xffe05000 0 0x1000>;
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 pcie@0 {
[all …]
H A Dp1020rdb.dts18 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
22 0x1 0x0 0x0 0xffa00000 0x00040000
23 0x2 0x0 0x0 0xffb00000 0x00020000>;
27 ranges = <0x0 0x0 0xffe00000 0x100000>;
31 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
33 reg = <0 0xffe09000 0 0x1000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1020rdb_36b.dts18 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22 0x1 0x0 0xf 0xffa00000 0x00040000
23 0x2 0x0 0xf 0xffb00000 0x00020000>;
27 ranges = <0x0 0xf 0xffe00000 0x100000>;
31 reg = <0xf 0xffe09000 0 0x1000>;
32 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
34 pcie@0 {
35 ranges = <0x2000000 0x0 0xc0000000
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-som-p0.dtsi16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17 <0x00000008 0x80000000 0x00000000 0x80000000>;
26 reg = <0x00 0x9e800000 0x00 0x01800000>;
27 alignment = <0x1000>;
33 reg = <0x00 0xa0000000 0x00 0x100000>;
39 reg = <0x00 0xa0100000 0x00 0xf00000>;
45 reg = <0x00 0xa1000000 0x00 0x100000>;
51 reg = <0x00 0xa1100000 0x00 0xf00000>;
57 reg = <0x00 0xa2000000 0x00 0x100000>;
63 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa0000000 0x00 0x100000>;
37 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 reg = <0x00 0xa1000000 0x00 0x100000>;
49 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 reg = <0x00 0xa2000000 0x00 0x100000>;
61 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc0_cfg_masks.h23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0
24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF
27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0
28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF
31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0
32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF
35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0
36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7
38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00
40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000
[all …]
/openbmc/linux/arch/arm/boot/dts/unisoc/
H A Drda8810pl.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
30 reg = <0x100000 0x10000>;
40 ranges = <0x0 0x10000000 0xfffffff>;
44 reg = <0x1a08000 0x1000>;
55 ranges = <0x0 0x20800000 0x100000>;
57 intc: interrupt-controller@0 {
59 reg = <0x0 0x1000>;
69 ranges = <0x0 0x20900000 0x100000>;
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-98dx3236.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
[all …]

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