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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am65.dtsi59 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
60 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
61 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
62 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
63 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
65 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
66 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
67 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
68 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
69 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dhardware.h26 #define KS2_DDRPHY_PIR_OFFSET 0x04
27 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
28 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
29 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
30 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
31 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
32 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
33 #define KS2_DDRPHY_PTR1_OFFSET 0x20
34 #define KS2_DDRPHY_PTR2_OFFSET 0x24
35 #define KS2_DDRPHY_PTR3_OFFSET 0x28
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dspeedstep-lib.c27 #define relaxed_check 0
40 [27, 25:22] (in MSR 0x2a) */ in pentium3_get_frequency()
42 { 30, 0x01 }, in pentium3_get_frequency()
43 { 35, 0x05 }, in pentium3_get_frequency()
44 { 40, 0x02 }, in pentium3_get_frequency()
45 { 45, 0x06 }, in pentium3_get_frequency()
46 { 50, 0x00 }, in pentium3_get_frequency()
47 { 55, 0x04 }, in pentium3_get_frequency()
48 { 60, 0x0b }, in pentium3_get_frequency()
49 { 65, 0x0f }, in pentium3_get_frequency()
[all …]
/openbmc/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/openbmc/linux/drivers/soc/tegra/cbb/
H A Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/openbmc/qemu/hw/mips/
H A Dmalta.c64 #define ENVP_PADDR 0x2000
70 #define FLASH_ADDRESS 0x1e000000ULL
71 #define FPGA_ADDRESS 0x1f000000ULL
72 #define RESET_ADDRESS 0x1fc00000ULL
74 #define FLASH_SIZE 0x400000
77 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
81 MemoryRegion iomem_lo; /* 0 - 0x900 */
82 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
125 for (i = 7 ; i >= 0 ; i--) { in malta_fpga_update_display_leds()
132 leds_text[8] = '\0'; in malta_fpga_update_display_leds()
[all …]