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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dti,am3359-adc.yaml27 description: List of analog inputs available for ADC. AIN0 = 0, AIN1 = 1 and
37 the start of ADC conversion. Maximum value is 0x3FFFF.
45 to sample (to hold start of conversion high). Maximum value is 0xFF.
72 ti,chan-step-opendelay = <0x098 0x3ffff 0x098 0x0>;
73 ti,chan-step-sampledelay = <0xff 0x0 0xf 0x0>;
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-com.h10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v3.h11 #define QSERDES_V3_COM_ATB_SEL1 0x000
12 #define QSERDES_V3_COM_ATB_SEL2 0x004
13 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
14 #define QSERDES_V3_COM_BG_TIMER 0x00c
15 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
16 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
17 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
18 #define QSERDES_V3_COM_SSC_PER1 0x01c
19 #define QSERDES_V3_COM_SSC_PER2 0x020
20 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v5.h10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v4.h10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v4.h10 #define QPHY_V4_PCS_SW_RESET 0x000
11 #define QPHY_V4_PCS_REVISION_ID0 0x004
12 #define QPHY_V4_PCS_REVISION_ID1 0x008
13 #define QPHY_V4_PCS_REVISION_ID2 0x00c
14 #define QPHY_V4_PCS_REVISION_ID3 0x010
15 #define QPHY_V4_PCS_PCS_STATUS1 0x014
16 #define QPHY_V4_PCS_PCS_STATUS2 0x018
17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
18 #define QPHY_V4_PCS_PCS_STATUS4 0x020
19 #define QPHY_V4_PCS_PCS_STATUS5 0x024
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am68-sk-som.dtsi15 reg = <0x00 0x80000000 0x00 0x80000000>,
16 <0x08 0x80000000 0x03 0x80000000>;
25 reg = <0x00 0x9e800000 0x00 0x01800000>;
34 J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
35 J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
43 pinctrl-0 = <&wkup_i2c0_pins_default>;
49 reg = <0x51>;
H A Dk3-j721s2-evm-gesi-exp-board.dtso27 J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
28 J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
34 J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
35 J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
36 J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
37 J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
38 J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
39 J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
40 J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
41 J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
[all …]
/openbmc/linux/drivers/clk/meson/
H A Daxg-audio.h16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_PAD_CTRL0 0x01c
24 #define AUDIO_MST_PAD_CTRL1 0x020
25 #define AUDIO_SW_RESET 0x024
[all …]
H A Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
/openbmc/u-boot/include/power/
H A Dhi6553_pmic.h12 HI6553_VERSION_REG = 0x000,
13 HI6553_ENABLE2_LDO1_8 = 0x029,
20 HI6553_DISABLE6_XO_CLK = 0x036,
21 HI6553_PERI_EN_MARK = 0x040,
22 HI6553_BUCK2_REG1 = 0x04a,
23 HI6553_BUCK2_REG5 = 0x04e,
26 HI6553_BUCK3_REG3 = 0x054,
27 HI6553_BUCK3_REG5 = 0x056,
29 HI6553_BUCK4_REG2 = 0x05b,
30 HI6553_BUCK4_REG5 = 0x05e,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Drockchip_mipi_dsi.h17 * #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
18 * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr
19 * offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0
23 #define OFFSET_SHIFT 0
28 #define VERSION DSI_HOST_BITS(0x000, 32, 0)
29 #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
30 #define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8)
31 #define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0)
32 #define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0)
33 #define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Deeprom.h25 MT_EE_CHIP_ID = 0x000,
26 MT_EE_VERSION = 0x002,
27 MT_EE_MAC_ADDR = 0x004,
28 MT_EE_NIC_CONF_0 = 0x034,
29 MT_EE_NIC_CONF_1 = 0x036,
30 MT_EE_WIFI_CONF = 0x03e,
31 MT_EE_CALDATA_FLASH = 0x052,
32 MT_EE_TX0_2G_TARGET_POWER = 0x058,
33 MT_EE_TX0_5G_G0_TARGET_POWER = 0x070,
34 MT7663_EE_5G_RATE_POWER = 0x089,
[all …]
/openbmc/linux/drivers/scsi/cxlflash/
H A Dmain.h25 #define PCI_DEVICE_ID_IBM_CORSA 0x04F0
26 #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600
27 #define PCI_DEVICE_ID_IBM_BRIARD 0x0624
29 /* Since there is only one target, make it 0 */
30 #define CXLFLASH_TARGET 0
40 #define FC_MTIP_CMDCONFIG 0x010
41 #define FC_MTIP_STATUS 0x018
42 #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */
43 #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */
44 #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */
[all …]
/openbmc/qemu/hw/nvram/
H A Dnrf51_nvm.c7 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
31 * CODEPAGESIZE 0x010
32 * CODESIZE 0x014
33 * CLENR0 0x028
34 * PPFC 0x02C
35 * NUMRAMBLOCK 0x034
36 * SIZERAMBLOCKS 0x038
37 * SIZERAMBLOCK[0] 0x038
38 * SIZERAMBLOCK[1] 0x03C
39 * SIZERAMBLOCK[2] 0x040
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dga100.c46 nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0x00000003); in ga100_chan_stop()
54 const int gfid = 0; in ga100_chan_start()
56 nvkm_wr32(device, runl->chan + (chan->id * 4), 0x00000002); in ga100_chan_start()
57 nvkm_wr32(device, runl->addr + 0x0090, (gfid << 16) | chan->id); /* INTERNAL_DOORBELL. */ in ga100_chan_start()
65 nvkm_wr32(runl->fifo->engine.subdev.device, runl->chan + (chan->id * 4), 0xffffffff); in ga100_chan_unbind()
74 nvkm_wo32(chan->inst, 0x010, 0x0000face); in ga100_chan_ramfc_write()
75 nvkm_wo32(chan->inst, 0x030, 0x7ffff902); in ga100_chan_ramfc_write()
76 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); in ga100_chan_ramfc_write()
77 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16)); in ga100_chan_ramfc_write()
78 nvkm_wo32(chan->inst, 0x084, 0x20400000); in ga100_chan_ramfc_write()
[all …]
/openbmc/qemu/pc-bios/s390-ccw/
H A Ds390-arch.h28 #define PSW_MASK_IOINT 0x0200000000000000ULL
29 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
30 #define PSW_MASK_WAIT 0x0002000000000000ULL
31 #define PSW_MASK_EAMODE 0x0000000100000000ULL
32 #define PSW_MASK_BAMODE 0x0000000080000000ULL
33 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
39 PSWLegacy ipl_psw; /* 0x000 */
40 uint32_t ccw1[2]; /* 0x008 */
42 uint32_t ccw2[2]; /* 0x010 */
48 uint8_t pad1[0x80 - 0x18]; /* 0x018 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/openbmc/linux/drivers/firewire/
H A Dohci.h7 #define OHCI1394_Version 0x000
8 #define OHCI1394_GUID_ROM 0x004
9 #define OHCI1394_ATRetries 0x008
10 #define OHCI1394_CSRData 0x00C
11 #define OHCI1394_CSRCompareData 0x010
12 #define OHCI1394_CSRControl 0x014
13 #define OHCI1394_ConfigROMhdr 0x018
14 #define OHCI1394_BusID 0x01C
15 #define OHCI1394_BusOptions 0x020
16 #define OHCI1394_GUIDHi 0x024
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_pcie2.h5 #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
6 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
7 #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
8 #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
9 #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
10 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
11 #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
12 #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
13 #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
14 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
[all …]
/openbmc/linux/arch/arm/include/asm/hardware/
H A Diomd.h27 #define IOMD_CONTROL (0x000)
28 #define IOMD_KARTTX (0x004)
29 #define IOMD_KARTRX (0x004)
30 #define IOMD_KCTRL (0x008)
32 #define IOMD_IRQSTATA (0x010)
33 #define IOMD_IRQREQA (0x014)
34 #define IOMD_IRQCLRA (0x014)
35 #define IOMD_IRQMASKA (0x018)
37 #define IOMD_IRQSTATB (0x020)
38 #define IOMD_IRQREQB (0x024)
[all …]

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