11cd50181SJerome Brunet /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 21cd50181SJerome Brunet /* 31cd50181SJerome Brunet * Copyright (c) 2018 BayLibre, SAS. 41cd50181SJerome Brunet * Author: Jerome Brunet <jbrunet@baylibre.com> 51cd50181SJerome Brunet */ 61cd50181SJerome Brunet 71cd50181SJerome Brunet #ifndef __AXG_AUDIO_CLKC_H 81cd50181SJerome Brunet #define __AXG_AUDIO_CLKC_H 91cd50181SJerome Brunet 101cd50181SJerome Brunet /* 111cd50181SJerome Brunet * Audio Clock register offsets 121cd50181SJerome Brunet * 131cd50181SJerome Brunet * Register offsets from the datasheet must be multiplied by 4 before 141cd50181SJerome Brunet * to get the right offset 151cd50181SJerome Brunet */ 161cd50181SJerome Brunet #define AUDIO_CLK_GATE_EN 0x000 171cd50181SJerome Brunet #define AUDIO_MCLK_A_CTRL 0x004 181cd50181SJerome Brunet #define AUDIO_MCLK_B_CTRL 0x008 191cd50181SJerome Brunet #define AUDIO_MCLK_C_CTRL 0x00C 201cd50181SJerome Brunet #define AUDIO_MCLK_D_CTRL 0x010 211cd50181SJerome Brunet #define AUDIO_MCLK_E_CTRL 0x014 221cd50181SJerome Brunet #define AUDIO_MCLK_F_CTRL 0x018 2307500138SMaxime Jourdan #define AUDIO_MST_PAD_CTRL0 0x01c 2407500138SMaxime Jourdan #define AUDIO_MST_PAD_CTRL1 0x020 257cfefab6SJerome Brunet #define AUDIO_SW_RESET 0x024 261cd50181SJerome Brunet #define AUDIO_MST_A_SCLK_CTRL0 0x040 271cd50181SJerome Brunet #define AUDIO_MST_A_SCLK_CTRL1 0x044 281cd50181SJerome Brunet #define AUDIO_MST_B_SCLK_CTRL0 0x048 291cd50181SJerome Brunet #define AUDIO_MST_B_SCLK_CTRL1 0x04C 301cd50181SJerome Brunet #define AUDIO_MST_C_SCLK_CTRL0 0x050 311cd50181SJerome Brunet #define AUDIO_MST_C_SCLK_CTRL1 0x054 321cd50181SJerome Brunet #define AUDIO_MST_D_SCLK_CTRL0 0x058 331cd50181SJerome Brunet #define AUDIO_MST_D_SCLK_CTRL1 0x05C 341cd50181SJerome Brunet #define AUDIO_MST_E_SCLK_CTRL0 0x060 351cd50181SJerome Brunet #define AUDIO_MST_E_SCLK_CTRL1 0x064 361cd50181SJerome Brunet #define AUDIO_MST_F_SCLK_CTRL0 0x068 371cd50181SJerome Brunet #define AUDIO_MST_F_SCLK_CTRL1 0x06C 381cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_A_CTRL 0x080 391cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_B_CTRL 0x084 401cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_C_CTRL 0x088 411cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 421cd50181SJerome Brunet #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 431cd50181SJerome Brunet #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 441cd50181SJerome Brunet #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 451cd50181SJerome Brunet #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 461cd50181SJerome Brunet #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 471cd50181SJerome Brunet #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 481cd50181SJerome Brunet #define AUDIO_CLK_LOCKER_CTRL 0x0A8 491cd50181SJerome Brunet #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 501cd50181SJerome Brunet #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 5107500138SMaxime Jourdan #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 521cd50181SJerome Brunet 53be4fe445SJerome Brunet /* SM1 introduce new register and some shifts :( */ 54be4fe445SJerome Brunet #define AUDIO_CLK_GATE_EN1 0x004 55be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_A_CTRL 0x008 56be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_B_CTRL 0x00C 57be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_C_CTRL 0x010 58be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_D_CTRL 0x014 59be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_E_CTRL 0x018 60be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_F_CTRL 0x01C 61be4fe445SJerome Brunet #define AUDIO_SM1_MST_PAD_CTRL0 0x020 62be4fe445SJerome Brunet #define AUDIO_SM1_MST_PAD_CTRL1 0x024 63be4fe445SJerome Brunet #define AUDIO_SM1_SW_RESET0 0x028 64be4fe445SJerome Brunet #define AUDIO_SM1_SW_RESET1 0x02C 65be4fe445SJerome Brunet #define AUDIO_CLK81_CTRL 0x030 66be4fe445SJerome Brunet #define AUDIO_CLK81_EN 0x034 67cf52db45SJerome Brunet 681cd50181SJerome Brunet #endif /*__AXG_AUDIO_CLKC_H */ 69