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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx7d-pinctrl.yaml94 reg = <0x30330000 0x10000>;
98 <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>,
99 <0x0164 0x03D4 0x0000 0x1 0x0 0x76>;
105 reg = <0x302c0000 0x10000>;
110 <0x0008 0x0038 0x0000 0x0 0x0 0x59>,
111 <0x000C 0x003C 0x0000 0x0 0x0 0x59>;
/openbmc/linux/sound/soc/mediatek/mt2701/
H A Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/openbmc/phosphor-fan-presence/control/config_files/p10bmc/com.ibm.Hardware.Chassis.Model.Rainier2U/
H A Dpcie_cards.json5 "vendor_id": "0xFFFF",
6 "device_id": "0xFFFF",
7 "subsystem_vendor_id": "0xFFFF",
8 "subsystem_id": "0xFFFF",
13 "vendor_id": "0x1014",
14 "device_id": "0x04F2",
15 "subsystem_vendor_id": "0x1014",
16 "subsystem_id": "0x0007",
21 "vendor_id": "0x1014",
22 "device_id": "0x04F2",
[all …]
/openbmc/phosphor-fan-presence/control/config_files/p10bmc/com.ibm.Hardware.Chassis.Model.Rainier1S4U/
H A Dpcie_cards.json5 "vendor_id": "0xFFFF",
6 "device_id": "0xFFFF",
7 "subsystem_vendor_id": "0xFFFF",
8 "subsystem_id": "0xFFFF",
13 "vendor_id": "0x1014",
14 "device_id": "0x04F2",
15 "subsystem_vendor_id": "0x1014",
16 "subsystem_id": "0x0007",
21 "vendor_id": "0x1014",
22 "device_id": "0x04F2",
[all …]
/openbmc/linux/drivers/media/platform/samsung/s5p-g2d/
H A Dg2d-regs.h10 #define SOFT_RESET_REG 0x0000 /* Software reset reg */
11 #define INTEN_REG 0x0004 /* Interrupt Enable reg */
12 #define INTC_PEND_REG 0x000C /* Interrupt Control Pending reg */
13 #define FIFO_STAT_REG 0x0010 /* Command FIFO Status reg */
14 #define AXI_ID_MODE_REG 0x0014 /* AXI Read ID Mode reg */
15 #define CACHECTL_REG 0x0018 /* Cache & Buffer clear reg */
16 #define AXI_MODE_REG 0x001C /* AXI Mode reg */
19 #define BITBLT_START_REG 0x0100 /* BitBLT Start reg */
20 #define BITBLT_COMMAND_REG 0x0104 /* Command reg for BitBLT */
23 #define ROTATE_REG 0x0200 /* Rotation reg */
[all …]
/openbmc/phosphor-fan-presence/control/config_files/p10bmc/com.ibm.Hardware.Chassis.Model.Rainier4U/
H A Dpcie_cards.json5 "vendor_id": "0xFFFF",
6 "device_id": "0xFFFF",
7 "subsystem_vendor_id": "0xFFFF",
8 "subsystem_id": "0xFFFF",
13 "vendor_id": "0x1014",
14 "device_id": "0x04F2",
15 "subsystem_vendor_id": "0x1014",
16 "subsystem_id": "0x0007",
21 "vendor_id": "0x1014",
22 "device_id": "0x04F2",
[all …]
/openbmc/linux/drivers/media/platform/qcom/camss/
H A Dcamss-csiphy-3ph-1-0.c3 * camss-csiphy-3ph-1-0.c
5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n))
20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n))
22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n))
23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n))
24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4
25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5
26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n))
27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx7d-pinfunc.h18 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
24 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
25 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
26 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7d-pinfunc.h14 #define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
15 #define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
16 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
18 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
19 #define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
20 #define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
21 #define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
23 #define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
[all …]
/openbmc/linux/include/linux/mfd/mt6397/
H A Dregisters.h11 #define MT6397_CID 0x0100
12 #define MT6397_TOP_CKPDN 0x0102
13 #define MT6397_TOP_CKPDN_SET 0x0104
14 #define MT6397_TOP_CKPDN_CLR 0x0106
15 #define MT6397_TOP_CKPDN2 0x0108
16 #define MT6397_TOP_CKPDN2_SET 0x010A
17 #define MT6397_TOP_CKPDN2_CLR 0x010C
18 #define MT6397_TOP_GPIO_CKPDN 0x010E
19 #define MT6397_TOP_RST_CON 0x0114
20 #define MT6397_WRP_CKPDN 0x011A
[all …]
/openbmc/qemu/hw/display/
H A Dati_dbg.c11 {"MM_INDEX", 0x0000},
12 {"MM_DATA", 0x0004},
13 {"CLOCK_CNTL_INDEX", 0x0008},
14 {"CLOCK_CNTL_DATA", 0x000c},
15 {"BIOS_0_SCRATCH", 0x0010},
16 {"BUS_CNTL", 0x0030},
17 {"BUS_CNTL1", 0x0034},
18 {"GEN_INT_CNTL", 0x0040},
19 {"GEN_INT_STATUS", 0x0044},
20 {"CRTC_GEN_CNTL", 0x0050},
[all …]
H A Dati_regs.h17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18 * 0x0100-0x0eff Misc regs only accessible via mmio
19 * 0x0f00-0x0fff Read-only copy of PCI config regs
20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21 * 0x1400-0x1fff GUI (drawing engine) regs
29 #define MM_INDEX 0x0000
30 #define MM_DATA 0x0004
31 #define CLOCK_CNTL_INDEX 0x0008
32 #define CLOCK_CNTL_DATA 0x000c
33 #define BIOS_0_SCRATCH 0x0010
[all …]
/openbmc/linux/include/linux/mfd/mt6323/
H A Dregisters.h10 #define MT6323_CHR_CON0 0x0000
11 #define MT6323_CHR_CON1 0x0002
12 #define MT6323_CHR_CON2 0x0004
13 #define MT6323_CHR_CON3 0x0006
14 #define MT6323_CHR_CON4 0x0008
15 #define MT6323_CHR_CON5 0x000A
16 #define MT6323_CHR_CON6 0x000C
17 #define MT6323_CHR_CON7 0x000E
18 #define MT6323_CHR_CON8 0x0010
19 #define MT6323_CHR_CON9 0x0012
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/openbmc/linux/include/video/
H A Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/openbmc/u-boot/board/ti/dra7xx/
H A Dmux_data.h321 {MCASP1_FSX, (M14 | 0x000d0000)}, /* mcasp1_fsx.gpio7_30 */
384 {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
385 {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
386 {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
387 {0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
388 {0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
389 {0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
390 {0x740, 0, 220}, /* RGMMI0_TXC_OUT */
391 {0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
392 {0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
[all …]
/openbmc/linux/drivers/net/wireless/zydas/zd1211rw/
H A Dzd_chip.h24 CR_START = 0x9000,
28 FW_START = 0xee00,
32 E2P_START = 0xf800,
33 E2P_LEN = 0x800,
36 E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */
37 E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */
39 E2P_DATA_LEN = 0x7e, /* base 0xf817 */
40 E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */
41 E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */
53 #define ZD_CR0 CTL_REG(0x0000)
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dmx7d_pins.h12 …0__GPIO1_IO0 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, …
13 MX7D_PAD_GPIO1_IO00__PWM4_OUT = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
14 …0__WDOG1_WDOG_B = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, …
16 …1__GPIO1_IO1 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, …
17 …1__PWM1_OUT = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, …
18 …1__CCM_ENET_REF_CLK3 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, …
19 …MX7D_PAD_GPIO1_IO01__SAI1_MCLK = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0…
21 …2__GPIO1_IO2 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, …
22 …2__PWM2_OUT = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, …
23 …2__CCM_ENET_REF_CLK1 = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, …
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHal8723BReg.h28 /* 0x0000h ~ 0x00FFh System Configuration */
31 #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */
32 #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */
33 #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */
34 #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */
35 #define REG_9346CR_8723B 0x000A /* 2 Byte */
36 #define REG_EE_VPD_8723B 0x000C /* 2 Byte */
37 #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */
38 #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */
39 #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */
[all …]
/openbmc/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/openbmc/u-boot/board/ti/am57xx/
H A Dmux_data.h1005 {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
1006 {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
1007 {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
1008 {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
1009 {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
1010 {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
1011 {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
1012 {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
1013 {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
1014 {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
[all …]
/openbmc/qemu/hw/misc/
H A Dexynos4210_pmu.c35 #define DEBUG_PMU 0
39 #define DEBUG_PMU_EXTEND 0
46 } while (0)
52 } while (0)
54 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
58 #define PRINT_DEBUG(fmt, args...) do {} while (0)
59 #define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0)
65 #define OM_STAT 0x0000 /* OM status register */
66 #define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */
67 #define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dmx6dl_pins.h9 MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10, 0x0360, 0x004C, 0, 0x0000, 0, 0)
10 MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC, 0x0360, 0x004C, 1, 0x0000, 0, 0)
11 MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO, 0x0360, 0x004C, 2, 0x07F8, 0, 0)
12 MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA, 0x0360, 0x004C, 3, 0x0000, 0, 0)
13 MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA, 0x0360, 0x004C, 3, 0x08FC, 0, 0)
14 MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28, 0x0360, 0x004C, 5, 0x0000, 0, 0)
15 MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07, 0x0360, 0x004C, 7, 0x0000, 0, 0)
16 MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11, 0x0364, 0x0050, 0, 0x0000, 0, 0)
17 MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS, 0x0364, 0x0050, 1, 0x0000, 0, 0)
18 MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0, 0x0364, 0x0050, 2, 0x0800, 0, 0)
[all …]
H A Dmx6q_pins.h11 MX6_PAD_DECL(SD2_DAT1__SD2_DATA1, 0x0360, 0x004C, 0, 0x0000, 0, 0)
12 MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0, 0x0360, 0x004C, 1, 0x0834, 0, 0)
13 MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B, 0x0360, 0x004C, 2, 0x0000, 0, 0)
14 MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS, 0x0360, 0x004C, 3, 0x07C8, 0, 0)
15 MX6_PAD_DECL(SD2_DAT1__KEY_COL7, 0x0360, 0x004C, 4, 0x08F0, 0, 0)
16 MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14, 0x0360, 0x004C, 5, 0x0000, 0, 0)
17 MX6_PAD_DECL(SD2_DAT2__SD2_DATA2, 0x0364, 0x0050, 0, 0x0000, 0, 0)
18 MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1, 0x0364, 0x0050, 1, 0x0838, 0, 0)
19 MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B, 0x0364, 0x0050, 2, 0x0000, 0, 0)
20 MX6_PAD_DECL(SD2_DAT2__AUD4_TXD, 0x0364, 0x0050, 3, 0x07B8, 0, 0)
[all …]

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