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/openbmc/linux/drivers/media/usb/gspca/
H A Ddtcs033.c32 if (gspca_dev->usb_err < 0) in reg_rw()
36 usb_rcvctrlpipe(udev, 0), in reg_rw()
42 if (ret < 0) { in reg_rw()
53 int i = 0; in reg_reqs()
56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs()
63 if (gspca_dev->usb_err < 0) { in reg_reqs()
111 return 0; in sd_config()
117 return 0; in sd_init()
137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan()
141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcm1_7xx.h23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
[all …]
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_hcd.h24 #define MUSB_CONTROL_EP 0
42 #define RH_INTERFACE 0x01
43 #define RH_ENDPOINT 0x02
44 #define RH_OTHER 0x03
46 #define RH_CLASS 0x20
47 #define RH_VENDOR 0x40
50 #define RH_GET_STATUS 0x0080
51 #define RH_CLEAR_FEATURE 0x0100
52 #define RH_SET_FEATURE 0x0300
53 #define RH_SET_ADDRESS 0x0500
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dwlf,wm8903.yaml48 default: 0
63 If any entry has the value 0xffffffff, that GPIO's
91 #size-cells = <0>;
95 reg = <0x1a>;
106 micdet-cfg = <0>;
109 0x0600 /* DMIC_LR, output */
110 0x0680 /* DMIC_DAT, input */
111 0x0000 /* GPIO, output, low */
112 0x0200 /* Interrupt, output */
113 0x01a0 /* BCLK, input, active high */
/openbmc/u-boot/drivers/usb/host/
H A Dsl811.h11 #define PDEBUG(level, fmt, args...) do {} while(0)
15 #define SL811_CTRL_A 0x00
16 #define SL811_ADDR_A 0x01
17 #define SL811_LEN_A 0x02
18 #define SL811_STS_A 0x03 /* read */
19 #define SL811_PIDEP_A 0x03 /* write */
20 #define SL811_CNT_A 0x04 /* read */
21 #define SL811_DEV_A 0x04 /* write */
22 #define SL811_CTRL1 0x05
23 #define SL811_INTR 0x06
[all …]
H A Dohci.h44 #define ED_NEW 0x00
45 #define ED_UNLINK 0x01
46 #define ED_OPER 0x02
47 #define ED_DEL 0x04
48 #define ED_URB_DEL 0x08
75 #define TD_CC 0xf0000000
76 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
77 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
78 #define TD_EC 0x0C000000
79 #define TD_T 0x03000000
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/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_pch.h19 PCH_NONE = 0, /* No PCH present */
35 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
36 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
37 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
38 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
39 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
40 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
41 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
42 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
43 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
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/openbmc/linux/drivers/video/fbdev/kyro/
H A DSTG4000Reg.h54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-usb2.c3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
45 PHY_STATE_HS_ONLINE = 0,
64 USB_CHG_STATE_UNDEFINED = 0,
224 * struct rockchip_usb2phy - usb2.0 phy driver data.
306 return 0; in rockchip_usb2phy_reset()
326 return 0; in rockchip_usb2phy_clk480m_prepare()
376 int ret = 0; in rockchip_usb2phy_clk480m_register()
378 init.flags = 0; in rockchip_usb2phy_clk480m_register()
391 init.num_parents = 0; in rockchip_usb2phy_clk480m_register()
404 if (ret < 0) in rockchip_usb2phy_clk480m_register()
[all …]
/openbmc/linux/sound/pci/cs46xx/
H A Ddsp_spos.h18 #define DSP_CODE_BYTE_SIZE 0x00007000UL
19 #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
20 #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
21 #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
22 #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
23 #define DSP_CODE_BYTE_OFFSET 0x00020000UL
25 #define WIDE_INSTR_MASK 0x0040
26 #define WIDE_LADD_INSTR_MASK 0x0380
32 WIDE_FOR_BEGIN_LOOP = 0x20,
35 WIDE_COND_GOTO_ADDR = 0x30,
[all …]
/openbmc/qemu/include/hw/pci/
H A Dpci_ids.h16 #define PCI_CLASS_NOT_DEFINED 0x0000
17 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
19 #define PCI_BASE_CLASS_STORAGE 0x01
20 #define PCI_CLASS_STORAGE_SCSI 0x0100
21 #define PCI_CLASS_STORAGE_IDE 0x0101
22 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
23 #define PCI_CLASS_STORAGE_IPI 0x0103
24 #define PCI_CLASS_STORAGE_RAID 0x0104
25 #define PCI_CLASS_STORAGE_ATA 0x0105
26 #define PCI_CLASS_STORAGE_SATA 0x0106
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/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_cmd_parser.c28 ST(0x1200, 1),
29 ST(0x1228, 1),
30 ST(0x1238, 1),
31 ST(0x1284, 1),
32 ST(0x128c, 1),
33 ST(0x1304, 1),
34 ST(0x1310, 1),
35 ST(0x1318, 1),
36 ST(0x12800, 4),
37 ST(0x128a0, 4),
[all …]
/openbmc/linux/arch/ia64/include/uapi/asm/
H A Dptrace_offsets.h77 #define PT_F32 0x0000
78 #define PT_F33 0x0010
79 #define PT_F34 0x0020
80 #define PT_F35 0x0030
81 #define PT_F36 0x0040
82 #define PT_F37 0x0050
83 #define PT_F38 0x0060
84 #define PT_F39 0x0070
85 #define PT_F40 0x0080
86 #define PT_F41 0x0090
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-clps711x.c19 #define CLPS711X_INTSR1 (0x0240)
20 #define CLPS711X_INTMR1 (0x0280)
21 #define CLPS711X_BLEOI (0x0600)
22 #define CLPS711X_MCEOI (0x0640)
23 #define CLPS711X_TEOI (0x0680)
24 #define CLPS711X_TC1EOI (0x06c0)
25 #define CLPS711X_TC2EOI (0x0700)
26 #define CLPS711X_RTCEOI (0x0740)
27 #define CLPS711X_UMSEOI (0x0780)
28 #define CLPS711X_COEOI (0x07c0)
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igbvf/
H A Digbvf.h28 lowest_latency = 0,
35 #define IGBVF_INT_MODE_LEGACY 0
54 * Setting this to 0 disables RX descriptor prefetch.
57 * If PTHRESH is 0, this should also be 0.
66 /* this is the size past which hardware will drop packets when setting LPE=0 */
69 #define IGBVF_FC_PAUSE_TIME 0x0680 /* 858 usec */
76 #define AUTO_ALL_MODES 0
77 #define IGBVF_EEPROM_APME 0x0400
268 #define IGBVF_FLAG_RX_CSUM_DISABLED BIT(0)
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv25.c36 NVKM_MEM_TARGET_INST, 0x3724, 16, true, in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111); in nv25_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080); in nv25_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); in nv25_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x04d0, 0x00000001); in nv25_gr_chan_new()
[all …]
H A Dnv30.c37 NVKM_MEM_TARGET_INST, 0x5f48, 16, true, in nv30_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv30_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060); in nv30_gr_chan_new()
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080); in nv30_gr_chan_new()
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000); in nv30_gr_chan_new()
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001); in nv30_gr_chan_new()
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000); in nv30_gr_chan_new()
51 nvkm_wo32(chan->inst, 0x048c, 0xffff0000); in nv30_gr_chan_new()
[all …]
/openbmc/linux/arch/parisc/include/asm/
H A Dropes.h47 #if DELAYED_RESOURCE_CNT > 0
56 #define SBA_SEARCH_SAMPLE 0x100
92 #define ASTRO_RUNWAY_PORT 0x582
93 #define IKE_MERCED_PORT 0x803
94 #define REO_MERCED_PORT 0x804
95 #define REOG_MERCED_PORT 0x805
96 #define PLUTO_MCKINLEY_PORT 0x880
114 #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
116 #define SBA_AGPGART_COOKIE (__force __le64) 0x0000badbadc0ffeeULL
118 #define SBA_FUNC_ID 0x0000 /* function id */
[all …]
/openbmc/qemu/hw/pci-host/
H A Dastro.c94 case 0x0008: in elroy_chip_read_with_attrs()
95 val = 0x6000005; /* func_class */ in elroy_chip_read_with_attrs()
97 case 0x0058: in elroy_chip_read_with_attrs()
106 case 0x0080: in elroy_chip_read_with_attrs()
109 case 0x0108: in elroy_chip_read_with_attrs()
112 case 0x200 ... 0x250 - 1: /* LMMIO, GMMIO, WLMMIO, WGMMIO, ... */ in elroy_chip_read_with_attrs()
113 index = (addr - 0x200) / 8; in elroy_chip_read_with_attrs()
116 case 0x0680: in elroy_chip_read_with_attrs()
119 case 0x0688: in elroy_chip_read_with_attrs()
120 val = 0; /* ERROR_STATUS */ in elroy_chip_read_with_attrs()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6ul-pinfunc.h17 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
18 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
24 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
25 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
26 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
27 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/openbmc/linux/include/linux/mfd/
H A Dmotorola-cpcap.h17 #define CPCAP_VENDOR_ST 0
21 #define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
23 #define CPCAP_REVISION_1_0 0x08
24 #define CPCAP_REVISION_1_1 0x09
25 #define CPCAP_REVISION_2_0 0x10
26 #define CPCAP_REVISION_2_1 0x11
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
[all …]
/openbmc/qemu/hw/alpha/
H A Dtyphoon.c81 uint64_t ret = 0; in cchip_read()
84 case 0x0000: in cchip_read()
87 PIP<14> Pchip 1 Present = 0. */ in cchip_read()
90 case 0x0040: in cchip_read()
95 case 0x0080: in cchip_read()
100 case 0x00c0: in cchip_read()
104 case 0x0100: /* AAR0 */ in cchip_read()
105 case 0x0140: /* AAR1 */ in cchip_read()
106 case 0x0180: /* AAR2 */ in cchip_read()
107 case 0x01c0: /* AAR3 */ in cchip_read()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHal8723BReg.h28 /* 0x0000h ~ 0x00FFh System Configuration */
31 #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */
32 #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */
33 #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */
34 #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */
35 #define REG_9346CR_8723B 0x000A /* 2 Byte */
36 #define REG_EE_VPD_8723B 0x000C /* 2 Byte */
37 #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */
38 #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */
39 #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A De1000.h42 #define E1000E_INT_MODE_LEGACY 0
58 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
64 #define AUTO_ALL_MODES 0
65 #define E1000_EEPROM_APME 0x0400
79 #define PCICFG_DESC_RING_STATUS 0xe4
80 #define FLUSH_DESC_REQUIRED 0x100
92 0x1f) /* pthresh */
95 (0x01000000 | /* set descriptor granularity */ \
98 0x20) /* set hthresh */
355 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
[all …]

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