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/openbmc/linux/drivers/mtd/chips/
H A Djedec_probe.c27 #define AM29DL800BB 0x22CB
28 #define AM29DL800BT 0x224A
30 #define AM29F800BB 0x2258
31 #define AM29F800BT 0x22D6
32 #define AM29LV400BB 0x22BA
33 #define AM29LV400BT 0x22B9
34 #define AM29LV800BB 0x225B
35 #define AM29LV800BT 0x22DA
36 #define AM29LV160DT 0x22C4
37 #define AM29LV160DB 0x2249
[all …]
/openbmc/u-boot/drivers/mtd/
H A Djedec_flash.c23 #define AM29DL800BB 0x22CB
24 #define AM29DL800BT 0x224A
26 #define AM29F400BB 0x22AB
27 #define AM29F800BB 0x2258
28 #define AM29F800BT 0x22D6
29 #define AM29LV400BB 0x22BA
30 #define AM29LV400BT 0x22B9
31 #define AM29LV800BB 0x225B
32 #define AM29LV800BT 0x22DA
33 #define AM29LV160DT 0x22C4
[all …]
/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/include/uapi/asm-generic/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpam.h35 * 0xa0000 - 0xbffff compatible SMRAM
37 * 0xc0000 - 0xc3fff Expansion area memory segments
38 * 0xc4000 - 0xc7fff
39 * 0xc8000 - 0xcbfff
40 * 0xcc000 - 0xcffff
41 * 0xd0000 - 0xd3fff
42 * 0xd4000 - 0xd7fff
43 * 0xd8000 - 0xdbfff
44 * 0xdc000 - 0xdffff
45 * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
[all …]
H A Dq35.h80 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
81 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
84 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
86 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
88 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
89 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
92 #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
93 #define MCH_HOST_BRIDGE_F_SMBASE 0x9c
94 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
95 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
[all …]
/openbmc/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/openbmc/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
/openbmc/linux/arch/alpha/include/uapi/asm/
H A Dtermbits.h54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
H A Dmman.h5 #define PROT_READ 0x1 /* page can be read */
6 #define PROT_WRITE 0x2 /* page can be written */
7 #define PROT_EXEC 0x4 /* page can be executed */
8 #define PROT_SEM 0x8 /* page may be used for atomic ops */
9 #define PROT_NONE 0x0 /* page can not be accessed */
10 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
11 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
13 /* 0x01 - 0x03 are defined in linux/mman.h */
14 #define MAP_TYPE 0x0f /* Mask for type of mapping (OSF/1 is _wrong_) */
15 #define MAP_FIXED 0x100 /* Interpret addr exactly */
[all …]
/openbmc/u-boot/drivers/bios_emulator/
H A Dbiosemu.c52 BE_sysEnv _BE_env = {{0}};
71 #define OFF(addr) (u16)(((addr) >> 0) & 0xffff)
72 #define SEG(addr) (u16)(((addr) >> 4) & 0xf000)
82 BIOS image as the BIOS that is used and emulated at 0xC0000.
90 memset(&M, 0, sizeof(M)); in BE_init()
93 return 0; in BE_init()
100 return 0; in BE_init()
104 _BE_env.emulateVGA = 0; in BE_init()
108 return 0; in BE_init()
142 _BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen - 1; in BE_setVGA()
[all …]
/openbmc/linux/arch/sparc/include/uapi/asm/
H A Dtermbits.h51 #define VINTR 0
78 #define IUCLC 0x0200
79 #define IXON 0x0400
80 #define IXOFF 0x1000
81 #define IMAXBEL 0x2000
82 #define IUTF8 0x4000
85 #define OLCUC 0x00002
86 #define ONLCR 0x00004
87 #define NLDLY 0x00100
88 #define NL0 0x00000
[all …]
/openbmc/qemu/linux-user/alpha/
H A Dtarget_mman.h4 #define TARGET_MAP_ANONYMOUS 0x10
5 #define TARGET_MAP_FIXED 0x100
6 #define TARGET_MAP_GROWSDOWN 0x01000
7 #define TARGET_MAP_DENYWRITE 0x02000
8 #define TARGET_MAP_EXECUTABLE 0x04000
9 #define TARGET_MAP_LOCKED 0x08000
10 #define TARGET_MAP_NORESERVE 0x10000
11 #define TARGET_MAP_POPULATE 0x20000
12 #define TARGET_MAP_NONBLOCK 0x40000
13 #define TARGET_MAP_STACK 0x80000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/
H A Dimx-regs.h9 #define LPUART_BASE 0x5A060000
11 #define GPT1_BASE_ADDR 0x5D140000
12 #define SCU_LPUART_BASE 0x33220000
13 #define GPIO1_BASE_ADDR 0x5D080000
14 #define GPIO2_BASE_ADDR 0x5D090000
15 #define GPIO3_BASE_ADDR 0x5D0A0000
16 #define GPIO4_BASE_ADDR 0x5D0B0000
17 #define GPIO5_BASE_ADDR 0x5D0C0000
18 #define GPIO6_BASE_ADDR 0x5D0D0000
19 #define GPIO7_BASE_ADDR 0x5D0E0000
[all …]
/openbmc/linux/tools/arch/alpha/include/uapi/asm/
H A Dmman.h13 #define MADV_NORMAL 0
19 #define MAP_ANONYMOUS 0x10
20 #define MAP_DENYWRITE 0x02000
21 #define MAP_EXECUTABLE 0x04000
22 #define MAP_FILE 0
23 #define MAP_FIXED 0x100
24 #define MAP_GROWSDOWN 0x01000
25 #define MAP_HUGETLB 0x100000
26 #define MAP_LOCKED 0x08000
27 #define MAP_NONBLOCK 0x40000
[all …]
/openbmc/linux/arch/x86/events/
H A Dperf_event_flags.h5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
/openbmc/linux/arch/alpha/include/asm/
H A Dsetup.h12 #define BOOT_PCB 0x20000000
13 #define BOOT_ADDR 0x20000000
18 #define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
20 #define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
25 #define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
26 #define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
27 #define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
28 #define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
30 #define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
39 #define COMMAND_LINE ((char *)(absolute_pointer(PARAM + 0x0000)))
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dlapic.h11 #define LAPIC_DEFAULT_BASE 0xfee00000
13 #define LAPIC_ID 0x020
14 #define LAPIC_LVR 0x030
16 #define LAPIC_TASKPRI 0x080
17 #define LAPIC_TPRI_MASK 0xff
19 #define LAPIC_RRR 0x0c0
21 #define LAPIC_SPIV 0x0f0
22 #define LAPIC_SPIV_ENABLE 0x100
24 #define LAPIC_ICR 0x300
25 #define LAPIC_DEST_SELF 0x40000
[all …]
/openbmc/qemu/include/hw/misc/
H A Dlasi.h22 #define LASI_IRR 0x00 /* RO */
23 #define LASI_IMR 0x04
24 #define LASI_IPR 0x08
25 #define LASI_ICR 0x0c
26 #define LASI_IAR 0x10
28 #define LASI_LPT 0x02000
29 #define LASI_AUDIO 0x04000
30 #define LASI_UART 0x05000
31 #define LASI_LAN 0x07000
32 #define LASI_RTC 0x09000
[all …]
/openbmc/linux/tools/testing/selftests/kvm/include/x86_64/
H A Dapic.h15 #define APIC_DEFAULT_GPA 0xfee00000ULL
18 #define MSR_IA32_APICBASE 0x0000001b
22 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
25 #define APIC_BASE_MSR 0x800
27 #define APIC_ID 0x20
28 #define APIC_LVR 0x30
29 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)
30 #define APIC_TASKPRI 0x80
31 #define APIC_PROCPRI 0xA0
32 #define APIC_EOI 0xB0
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c19 #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200)
26 #define SPEAR1340_PLL_CFG (misc_base + 0x210)
38 #define SPEAR1340_PLL1_CTR (misc_base + 0x214)
39 #define SPEAR1340_PLL1_FRQ (misc_base + 0x218)
40 #define SPEAR1340_PLL2_CTR (misc_base + 0x220)
41 #define SPEAR1340_PLL2_FRQ (misc_base + 0x224)
42 #define SPEAR1340_PLL3_CTR (misc_base + 0x22C)
43 #define SPEAR1340_PLL3_FRQ (misc_base + 0x230)
44 #define SPEAR1340_PLL4_CTR (misc_base + 0x238)
45 #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C)
[all …]
/openbmc/u-boot/include/configs/km/
H A Dkm-powerpc.h22 #define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
24 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
26 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
28 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
47 #define CONFIG_KM_ROOTFSSIZE 0x0
49 #define CONFIG_KM_PNVRAM 0x80000
51 #define CONFIG_KM_PHRAM 0x100000
53 #define CONFIG_KM_RESERVED_PRAM 0x0
58 #define CONFIG_KM_CRAMFS_ADDR 0xC00000
59 #define CONFIG_KM_KERNEL_ADDR 0x400000 /* 7680Kbytes */
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dmips-gic.h20 #define MIPS_GIC_SHARED_OFS 0x00000
21 #define MIPS_GIC_SHARED_SZ 0x08000
22 #define MIPS_GIC_LOCAL_OFS 0x08000
23 #define MIPS_GIC_LOCAL_SZ 0x04000
24 #define MIPS_GIC_REDIR_OFS 0x0c000
25 #define MIPS_GIC_REDIR_SZ 0x04000
26 #define MIPS_GIC_USER_OFS 0x10000
27 #define MIPS_GIC_USER_SZ 0x10000
105 return val & 0x1; \
164 GIC_ACCESSOR_RW(32, 0x000, config)
[all …]

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