Lines Matching +full:0 +full:x04000
80 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
81 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
84 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
86 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
88 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
89 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
92 #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
93 #define MCH_HOST_BRIDGE_F_SMBASE 0x9c
94 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
95 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
96 #define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02
98 #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
100 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
101 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */
105 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
106 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
107 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
108 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
109 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
114 #define MCH_HOST_BRIDGE_PAM0 0x90
115 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
116 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
117 #define MCH_HOST_BRIDGE_PAM1 0x91
118 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
119 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
120 #define MCH_HOST_BRIDGE_PAM2 0x92
121 #define MCH_HOST_BRIDGE_PAM3 0x93
122 #define MCH_HOST_BRIDGE_PAM4 0x94
123 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
124 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
125 #define MCH_HOST_BRIDGE_PAM5 0x95
126 #define MCH_HOST_BRIDGE_PAM6 0x96
127 #define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
128 #define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
129 #define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
130 #define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
131 #define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
132 #define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
133 #define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
134 #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
135 #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
137 #define MCH_HOST_BRIDGE_SMRAM 0x9d
143 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
144 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
145 #define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
146 #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
147 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
148 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
159 #define MCH_HOST_BRIDGE_ESMRAMC 0x9e
165 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
166 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
167 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
168 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
178 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0
182 #define MCH_PCIE_FUNC 0
189 #define Q35_PSEUDO_BUS_PLATFORM (0xff)
190 #define Q35_PSEUDO_DEVFN_IOAPIC (0x00)