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/openbmc/openbmc/meta-ibm/recipes-phosphor/configuration/p10bmc-yaml-config/
H A Dp10bmc-ipmi-inventory-sensors.yaml2 sensorID: 0x01
3 sensorType: 0x0C
4 eventReadingType: 0x6F
5 offset: 0x04
7 sensorID: 0x02
8 sensorType: 0x0C
9 eventReadingType: 0x6F
10 offset: 0x04
12 sensorID: 0x03
13 sensorType: 0x0C
[all …]
H A Dp10bmc-ipmi-sensors.yaml1 0x01:
2 entityID: 0x20
3 entityInstance: 0x01
8 0x04:
15 0x06:
20 0x04:
28 sensorReadingType: 0x6F
29 sensorType: 0x0C
31 0x02:
32 entityID: 0x20
[all …]
/openbmc/u-boot/include/
H A Dst_logo_data.h14 0x42, 0x4d, 0x5c, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x04,
15 0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x60, 0x01,
16 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe2, 0x93,
17 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x01,
18 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x42, 0x47, 0x52, 0x73, 0x00, 0x00,
19 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
21 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
22 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
23 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/openbmc/qemu/ebpf/
H A Drss.bpf.skeleton.h146 s->maps[0].name = "tap_rss_map_configurations"; in rss_bpf__create_skeleton()
147 s->maps[0].map = &obj->maps.tap_rss_map_configurations; in rss_bpf__create_skeleton()
164 s->progs[0].name = "tun_rss_steering_prog"; in rss_bpf__create_skeleton()
165 s->progs[0].prog = &obj->progs.tun_rss_steering_prog; in rss_bpf__create_skeleton()
166 s->progs[0].link = &obj->links.tun_rss_steering_prog; in rss_bpf__create_skeleton()
171 return 0; in rss_bpf__create_skeleton()
180 \x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
181 \0\0\0\0\0\0\0\0\0\0\0\xb0\x4b\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0d\0\ in rss_bpf__elf_bytes()
182 \x01\0\x7b\x1a\x48\xff\0\0\0\0\xb7\x09\0\0\0\0\0\0\x63\x9a\x54\xff\0\0\0\0\xbf\ in rss_bpf__elf_bytes()
183 \xa7\0\0\0\0\0\0\x07\x07\0\0\x54\xff\xff\xff\x18\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\ in rss_bpf__elf_bytes()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dcros-ec-keyboard.dtsi21 MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
22 MATRIX_KEY(0x00, 0x02, KEY_F1)
23 MATRIX_KEY(0x00, 0x03, KEY_B)
24 MATRIX_KEY(0x00, 0x04, KEY_F10)
25 MATRIX_KEY(0x00, 0x06, KEY_N)
26 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
27 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
29 MATRIX_KEY(0x01, 0x01, KEY_ESC)
30 MATRIX_KEY(0x01, 0x02, KEY_F4)
31 MATRIX_KEY(0x01, 0x03, KEY_G)
[all …]
H A Dexynos5420-peach-pit.dts35 pwms = <&pwm 0 1000000 0>;
36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
66 reg = <0x9>;
77 sound-dai = <&i2s0 0>;
81 sound-dai = <&max98090 0>;
88 reg = <0x10>;
95 reg = <0x48>;
99 0x02 0xa1 0x01 /* HPD low */
102 * [1:0] SW output 1.2V voltage is lower to 96%
104 0x04 0x14 0x01
[all …]
H A Dast2600-qcom-dc-scm-v1.dts13 reg = <0x80000000 0x40000000>;
27 cpu@0 {
60 pinctrl-0 = <&pinctrl_mdio4_default>;
62 #size-cells = <0>;
71 reg = <0x1e670000 0x180>, <0x1e650018 0x4>;
75 pinctrl-0 = <&pinctrl_rgmii3_default>;
82 pinctrl-0 = <&pinctrl_fmcquad_default>;
84 flash@0 {
103 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
107 flash@0 {
[all …]
H A Dtegra20-harmony.dts26 reg = <0x00000000 0x40000000>;
39 timing@0 {
70 pinctrl-0 = <&state_default>;
311 reg = <0x1a>;
318 micdet-cfg = <0>;
320 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
328 nand@0 {
329 reg = <0>;
350 reg = <0x34>;
471 reg = <0x4c>;
[all …]
/openbmc/u-boot/arch/sandbox/dts/
H A Dcros-ec-keyboard.dtsi21 MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
22 MATRIX_KEY(0x00, 0x02, KEY_F1)
23 MATRIX_KEY(0x00, 0x03, KEY_B)
24 MATRIX_KEY(0x00, 0x04, KEY_F10)
25 MATRIX_KEY(0x00, 0x06, KEY_N)
26 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
27 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
29 MATRIX_KEY(0x01, 0x01, KEY_ESC)
30 MATRIX_KEY(0x01, 0x02, KEY_F4)
31 MATRIX_KEY(0x01, 0x03, KEY_G)
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dvsx-ops.c.inc1 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
2 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
3 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
5 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
6 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
7 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
8 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
9 GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
[all …]
H A Dvmx-ops.c.inc2 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
5 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
8 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
11 GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
14 GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
18 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
21 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
24 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
25 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
27 GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE),
[all …]
H A Dspe-ops.c.inc1 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
2 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
3 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
4 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
7 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
8 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
12 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra20-gpio.txt11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
16 bits[3:0] trigger type and level flags:
28 reg = < 0x6000d000 0x1000 >;
29 interrupts = < 0 32 0x04
30 0 33 0x04
31 0 34 0x04
32 0 35 0x04
33 0 55 0x04
34 0 87 0x04
35 0 89 0x04 >;
/openbmc/openbmc/meta-quanta/meta-gbs/recipes-phosphor/ipmi/phosphor-ipmi-host/
H A Dgbs-ipmid-whitelist.conf2 0x00:0x00 //<Chassis>:<Chassis Capabiliti>
3 0x00:0x01 //<Chassis>:<Get Chassis Status>
4 0x00:0x02 //<Chassis>:<Chassis Control>
5 0x00:0x04 //<Chassis>:<Chassis Identify>
6 0x00:0x05 //<Chassis>:<Set Chassis Capabilities>
7 0x00:0x06 //<Chassis>:<Set Power Restore Policy>
8 0x00:0x08 //<Chassis>:<Set System Boot Options>
9 0x00:0x09 //<Chassis>:<Get System Boot Options>
10 0x00:0x0F //<Chassis>:<Get POH Counter>
11 0x04:0x02 //<Sensor/Event>:<Platform Event>
[all …]
/openbmc/phosphor-host-ipmid/scripts/
H A Dinventory-sensor-example.yaml2 sensorID: 0xa6
3 sensorType: 0x0C
4 eventReadingType: 0x6F
5 offset: 0x04
7 sensorID: 0xa8
8 sensorType: 0x0C
9 eventReadingType: 0x6F
10 offset: 0x04
12 sensorID: 0xba
13 sensorType: 0x0C
[all …]
/openbmc/openbmc/meta-phosphor/recipes-phosphor/ipmi/phosphor-ipmi-inventory-sel/
H A Dconfig.yaml2 sensorID: 0xa6
3 sensorType: 0x0C
4 eventReadingType: 0x6F
5 offset: 0x04
7 sensorID: 0xa8
8 sensorType: 0x0C
9 eventReadingType: 0x6F
10 offset: 0x04
12 sensorID: 0xba
13 sensorType: 0x0C
[all …]
/openbmc/openpower-host-ipmi-oem/scripts/
H A Dinventory-sensor-example.yaml2 sensorID: 0xa6
3 sensorType: 0x0C
4 eventReadingType: 0x6F
5 offset: 0x04
7 sensorID: 0xa8
8 sensorType: 0x0C
9 eventReadingType: 0x6F
10 offset: 0x04
12 sensorID: 0xba
13 sensorType: 0x0C
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5329.h17 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28)
18 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24)
19 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20)
20 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12)
21 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8)
22 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4)
28 #define BMT_BME (0x08)
29 #define BMT_8 (0x07)
30 #define BMT_16 (0x06)
31 #define BMT_32 (0x05)
[all …]
/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Deport.h15 u16 par; /* 0x00 */
16 u16 res0; /* 0x02 */
17 u8 ddr; /* 0x04 */
18 u8 ier; /* 0x05 */
19 u16 res1; /* 0x06 */
20 u8 dr; /* 0x08 */
21 u8 pdr; /* 0x09 */
22 u16 res2; /* 0x0A */
23 u8 fr; /* 0x0C */
24 u8 res3[3]; /* 0x0D */
[all …]
/openbmc/bmcweb/test/http/
H A Dhttp2_connection_test.cpp54 "curl/8.5.0"); in handle()
74 int inflateFlags = 0; in unpackHeaders()
79 ASSERT_GT(parsed, 0); in unpackHeaders()
81 if ((inflateFlags & NGHTTP2_HD_INFLATE_EMIT) > 0) in unpackHeaders()
89 if ((inflateFlags & NGHTTP2_HD_INFLATE_FINAL) > 0) in unpackHeaders()
91 EXPECT_EQ(inflater.endHeaders(), 0); in unpackHeaders()
111 "\x00\x00\x12\x04\x00\x00\x00\x00\x00" in TEST()
113 "\x00\x03\x00\x00\x00\x64\x00\x04\x00\xa0\x00\x00\x00\x02\x00\x00\x00\x00" in TEST()
115 "\x00\x00\x04\x08\x00\x00\x00\x00\x00" in TEST()
122 "\x04\x89\x62\xc2\xc9\x29\x91\x3b\x1d\xc2\xc7\x7a\x88\x25\xb6\x50" in TEST()
[all …]
/openbmc/qemu/hw/xen/
H A Dxen_pt_graphics.c13 #define XEN_PCI_INTEL_OPREGION_MASK 0xfff
23 #define IORESOURCE_IO 0x00000100
24 #define IORESOURCE_MEM 0x00000200
29 .guest_base_addr = 0x3B0,
30 .machine_base_addr = 0x3B0,
31 .size = 0xC,
36 .guest_base_addr = 0x3C0,
37 .machine_base_addr = 0x3C0,
38 .size = 0x20,
43 .guest_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
[all …]
/openbmc/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.h32 static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
33 {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
34 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
35 {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
36 {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
37 {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
38 {0x16, 0xA0} };
44 static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
45 {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
46 {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
[all …]
/openbmc/openbmc-test-automation/data/
H A Dipmi_raw_cmd_table.py25 "0x04 0x2d 0x0b",
35 "0x04 0x30 0x0b 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00",
37 "Enabled nibble position 6th LSB e.g. 0x2",
41 "0x04 0x30 0x0b 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00",
43 "Enabled nibble position 6th LSB e.g. 0x1",
49 "0x2c 0x02 0xdc 0x01 0x01 0x00",
57 "0x2c 0x12 0xdc 0x02 0x00 0x01",
59 "Enabled nibble position 6th LSB e.g. 0x01",
63 "0x2c 0x12 0xdc 0x02 0x00 0x00",
65 "Disable nibble position 6th LSB e.g. 0x00",
[all …]
/openbmc/qemu/tests/qtest/migration/aarch64/
H A Da-b-kernel.h7 0x00, 0x10, 0x38, 0xd5, 0x00, 0xf8, 0x7f, 0x92, 0x00, 0x10, 0x18, 0xd5,
8 0xdf, 0x3f, 0x03, 0xd5, 0x00, 0x02, 0xa8, 0xd2, 0x01, 0xc8, 0xa8, 0xd2,
9 0x23, 0x08, 0x80, 0x52, 0x02, 0x20, 0xa1, 0xd2, 0x43, 0x00, 0x00, 0x39,
10 0x03, 0x00, 0x80, 0x52, 0xe4, 0x03, 0x00, 0xaa, 0x83, 0x00, 0x00, 0x39,
11 0x84, 0x04, 0x40, 0x91, 0x9f, 0x00, 0x01, 0xeb, 0xad, 0xff, 0xff, 0x54,
12 0x05, 0x00, 0x80, 0x52, 0xe4, 0x03, 0x00, 0xaa, 0x83, 0x00, 0x40, 0x39,
13 0x63, 0x04, 0x00, 0x11, 0x83, 0x00, 0x00, 0x39, 0x24, 0x7e, 0x0b, 0xd5,
14 0x84, 0x04, 0x40, 0x91, 0x9f, 0x00, 0x01, 0xeb, 0x4b, 0xff, 0xff, 0x54,
15 0xa5, 0x04, 0x00, 0x11, 0xa5, 0x10, 0x00, 0x12, 0xbf, 0x00, 0x00, 0x71,
16 0xa1, 0xfe, 0xff, 0x54, 0x43, 0x08, 0x80, 0x52, 0x43, 0x00, 0x00, 0x39,
[all …]
/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_dpcd.h16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
[all …]

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