13 #define XEN_PCI_INTEL_OPREGION_MASK 0xfff
23 #define IORESOURCE_IO           0x00000100
24 #define IORESOURCE_MEM          0x00000200
29         .guest_base_addr = 0x3B0,
30         .machine_base_addr = 0x3B0,
31         .size = 0xC,
36         .guest_base_addr = 0x3C0,
37         .machine_base_addr = 0x3C0,
38         .size = 0x20,
43         .guest_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
44         .machine_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
45         .size = 0x20,
55     int i = 0;  in xen_pt_register_vga_regions()
58         return 0;  in xen_pt_register_vga_regions()
61     for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {  in xen_pt_register_vga_regions()
82     return 0;  in xen_pt_register_vga_regions()
90     int i = 0;  in xen_pt_unregister_vga_regions()
91     int ret = 0;  in xen_pt_unregister_vga_regions()
94         return 0;  in xen_pt_unregister_vga_regions()
97     for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {  in xen_pt_unregister_vga_regions()
129     return 0;  in xen_pt_unregister_vga_regions()
173     char checksum = 0;  in xen_pt_setup_vga()
174     uint32_t len = 0;  in xen_pt_setup_vga()
225     cpu_physical_memory_write(0xc0000, bios, bios_size);  in xen_pt_setup_vga()
230     uint32_t val = 0;  in igd_read_opregion()
242 #define XEN_PCI_INTEL_OPREGION_PAGES 0x3
243 #define XEN_PCI_INTEL_OPREGION_ENABLE_ACCESSED 0x1
267                     " 0x%lx.\n", ret,  in igd_write_opregion()
269         igd_guest_opregion = 0;  in igd_write_opregion()
280         XEN_PT_ERR(&s->dev, "[%d]:Can't map IGD host opregion:0x%lx to"  in igd_write_opregion()
281                     " guest opregion:0x%lx.\n", ret,  in igd_write_opregion()
284         igd_guest_opregion = 0;  in igd_write_opregion()
288     XEN_PT_LOG(&s->dev, "Map OpRegion: 0x%lx -> 0x%lx\n",  in igd_write_opregion()
312  * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell)
313  * scenarios, 0x9cc3 for BDW(Broadwell).
317     {0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */
318     {0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */
319     {0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */
320     {0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */
321     {0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */
323     {0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */
324     {0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */
325     {0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */
326     {0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */
327     {0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */
328     {0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */
330     {0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */
331     {0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */
333     {0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */
335     {0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */
337     {0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */
338     {0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */
339     {0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */
340     {0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */
341     {0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */
342     {0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */
343     {0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */
344     {0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */
345     {0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */
346     {0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */
347     {0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */
385     uint16_t pch_dev_id = 0xffff;  in type_init()
386     uint8_t pch_rev_id = 0;  in type_init()
389     for (i = 0; i < num; i++) {  in type_init()
396     if (pch_dev_id == 0xffff) {  in type_init()
400     /* Currently IGD drivers always need to access PCH by 1f.0. */  in type_init()
401     bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0),  in type_init()