Searched +full:0 +full:x033c0000 (Results 1 – 5 of 5) sorted by relevance
69 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"91 enum: [0, 1, 2, 3]92 default: 094 0: No adjustments133 reg = <0x033c0000 0x20000>,134 <0x03550000 0x10000>;142 gpio-ranges = <&lpass_tlmm 0 0 15>;
28 #define Q6SS_RESET_REG 0x01429 #define Q6SS_GFMUX_CTL_REG 0x02030 #define Q6SS_PWR_CTL_REG 0x03031 #define Q6SS_MEM_PWR_CTL 0x0B032 #define Q6SS_STRAP_ACC 0x11033 #define Q6SS_CGC_OVERRIDE 0x03434 #define Q6SS_BCR_REG 0x600037 #define AXI_HALTREQ_REG 0x038 #define AXI_HALTACK_REG 0x439 #define AXI_IDLE_REG 0x8[all …]
36 #clock-cells = <0>;44 #clock-cells = <0>;50 #size-cells = <0>;52 CPU0: cpu@0 {55 reg = <0x0 0x0>;56 clocks = <&cpufreq_hw 0>;59 qcom,freq-domain = <&cpufreq_hw 0>;79 reg = <0x0 0x100>;80 clocks = <&cpufreq_hw 0>;83 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
78 #clock-cells = <0>;84 #clock-cells = <0>;95 reg = <0x0 0x004cd000 0x0 0x1000>;99 reg = <0x0 0x80000000 0x0 0x600000>;104 reg = <0x0 0x80600000 0x0 0x200000>;109 reg = <0x0 0x80800000 0x0 0x60000>;114 reg = <0x0 0x80860000 0x0 0x20000>;120 reg = <0x0 0x80884000 0x0 0x10000>;125 reg = <0x0 0x808ff000 0x0 0x1000>;130 reg = <0x0 0x80900000 0x0 0x200000>;[all …]
81 #clock-cells = <0>;89 #clock-cells = <0>;95 #size-cells = <0>;97 CPU0: cpu@0 {100 reg = <0x0 0x0>;101 clocks = <&cpufreq_hw 0>;108 qcom,freq-domain = <&cpufreq_hw 0>;110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,116 cache-size = <0x20000>;122 cache-size = <0x400000>;[all …]