Searched +full:0 +full:x03300000 (Results 1 – 10 of 10) sorted by relevance
56 reg = <0x03300000 0x30000>;
46 port@0:57 - port@080 reg = <0x03300000 0x40000>;92 #size-cells = <0>;94 deu0_in: port@0 {95 reg = <0>;104 #size-cells = <0>;107 deu0_out_be0: endpoint@0 {108 reg = <0>;
17 qcom,board-id = <132 0x0a>;18 qcom,msm-id = <199 0x20000>;31 reg = <0x02f00000 0x100000>;36 reg = <0x03100000 0x200000>;41 reg = <0x03300000 0x1400000>;57 pinctrl-0 = <&wlan_regulator_default_state>;70 reg = <0x55>;80 reg = <0x20>;87 pinctrl-0 = <&touch_pins>;90 #size-cells = <0>;[all …]
25 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)27 (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)29 #define THEADORABLE_GPP_OUT_ENA_LOW 0x0033678030 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf031 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))33 #define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f34 #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c35 #define THEADORABLE_GPP_OUT_VAL_HIGH 0x0000000043 #define STM_I2C_ADDR 0x2748 {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */[all …]
28 #define Q6SS_RESET_REG 0x01429 #define Q6SS_GFMUX_CTL_REG 0x02030 #define Q6SS_PWR_CTL_REG 0x03031 #define Q6SS_MEM_PWR_CTL 0x0B032 #define Q6SS_STRAP_ACC 0x11033 #define Q6SS_CGC_OVERRIDE 0x03434 #define Q6SS_BCR_REG 0x600037 #define AXI_HALTREQ_REG 0x038 #define AXI_HALTACK_REG 0x439 #define AXI_IDLE_REG 0x8[all …]
61 #size-cells = <0>;63 cpu0: cpu@0 {69 reg = <0x0>;78 reg = <0x1>;87 reg = <0x2>;96 reg = <0x3>;105 reg = <0x100>;114 reg = <0x101>;123 reg = <0x102>;132 reg = <0x103>;[all …]
65 #size-cells = <0>;67 cpu0: cpu@0 {73 reg = <0x0>;82 reg = <0x1>;91 reg = <0x2>;100 reg = <0x3>;109 reg = <0x100>;118 reg = <0x101>;127 reg = <0x102>;136 reg = <0x103>;[all …]
27 #define ERRLOGGER_0_ID_COREID_0 0x0000000028 #define ERRLOGGER_0_ID_REVISIONID_0 0x0000000429 #define ERRLOGGER_0_FAULTEN_0 0x0000000830 #define ERRLOGGER_0_ERRVLD_0 0x0000000c31 #define ERRLOGGER_0_ERRCLR_0 0x0000001032 #define ERRLOGGER_0_ERRLOG0_0 0x0000001433 #define ERRLOGGER_0_ERRLOG1_0 0x0000001834 #define ERRLOGGER_0_RSVD_00_0 0x0000001c35 #define ERRLOGGER_0_ERRLOG3_0 0x0000002036 #define ERRLOGGER_0_ERRLOG4_0 0x00000024[all …]
78 #clock-cells = <0>;84 #clock-cells = <0>;95 reg = <0x0 0x004cd000 0x0 0x1000>;99 reg = <0x0 0x80000000 0x0 0x600000>;104 reg = <0x0 0x80600000 0x0 0x200000>;109 reg = <0x0 0x80800000 0x0 0x60000>;114 reg = <0x0 0x80860000 0x0 0x20000>;120 reg = <0x0 0x80884000 0x0 0x10000>;125 reg = <0x0 0x808ff000 0x0 0x1000>;130 reg = <0x0 0x80900000 0x0 0x200000>;[all …]
81 #clock-cells = <0>;89 #clock-cells = <0>;95 #size-cells = <0>;97 CPU0: cpu@0 {100 reg = <0x0 0x0>;101 clocks = <&cpufreq_hw 0>;108 qcom,freq-domain = <&cpufreq_hw 0>;110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,116 cache-size = <0x20000>;122 cache-size = <0x400000>;[all …]