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/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h15 #define CCM_GPR0_OFFSET 0x0
16 #define CCM_OBSERVE0_OFFSET 0x0400
17 #define CCM_SCTRL0_OFFSET 0x0800
18 #define CCM_CCGR0_OFFSET 0x4000
19 #define CCM_ROOT0_TARGET_OFFSET 0x8000
58 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
60 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
65 uint32_t ctrl_24m; /* offset 0x0000 */
69 uint32_t rcosc_config0; /* offset 0x0010 */
73 uint32_t rcosc_config1; /* offset 0x0020 */
[all …]
/openbmc/linux/arch/arm/mach-rpc/include/mach/
H A Dhardware.h25 #define RPC_RAM_SIZE 0x10000000
26 #define RPC_RAM_START 0x10000000
28 #define EASI_SIZE 0x08000000 /* EASI I/O */
29 #define EASI_START 0x08000000
30 #define EASI_BASE IOMEM(0xe5000000)
32 #define IO_START 0x03000000 /* I/O */
33 #define IO_SIZE 0x01000000
34 #define IO_BASE IOMEM(0xe0000000)
36 #define SCREEN_START 0x02000000 /* VRAM */
37 #define SCREEN_END 0xdfc00000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg94.c39 nvkm_mask(device, 0x61c128 + loff, 0x0000003f, watermark); in g94_sor_dp_watermark()
49 nvkm_mask(device, 0x61c10c + loff, 0x000001fc, TU << 2); in g94_sor_dp_activesym()
50 nvkm_mask(device, 0x61c128 + loff, 0x010f7f00, VTUa << 24 | VTUf << 16 | VTUi << 8); in g94_sor_dp_activesym()
59 nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h); in g94_sor_dp_audio_sym()
60 nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v); in g94_sor_dp_audio_sym()
71 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
72 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
73 data[2] = nvkm_rd32(device, 0x61c130 + loff); in g94_sor_dp_drive()
74 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0) in g94_sor_dp_drive()
75 data[2] = (data[2] & ~0x0000ff00) | (pu << 8); in g94_sor_dp_drive()
[all …]
/openbmc/u-boot/include/
H A Dmpc83xx.h23 #define EXC_OFF_SYS_RESET 0x0100
31 #define CONFIG_DEFAULT_IMMR 0xFF400000
34 #define IMMRBAR 0x0000
35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
42 #define LBLAWBAR0 0x0020
43 #define LBLAWAR0 0x0024
44 #define LBLAWBAR1 0x0028
45 #define LBLAWAR1 0x002C
46 #define LBLAWBAR2 0x0030
47 #define LBLAWAR2 0x0034
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Di740_reg.h37 #define XRX 0x3D6
38 #define MRX 0x3D2
41 #define DACMASK 0x3C6
42 #define DACSTATE 0x3C7
43 #define DACRX 0x3C7
44 #define DACWX 0x3C8
45 #define DACDATA 0x3C9
48 #define START_ADDR_HI 0x0C
49 #define START_ADDR_LO 0x0D
50 #define VERT_SYNC_END 0x11
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c33 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
49 { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
50 { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
51 { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
52 { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
53 { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
54 { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
55 { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
56 { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
57 { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
[all …]
/openbmc/u-boot/board/cadence/xtfpga/
H A DKconfig33 default 0x04000000 if XTFPGA_LX60
34 default 0x03000000 if XTFPGA_LX110
35 default 0x06000000 if XTFPGA_LX200
36 default 0x18000000 if XTFPGA_ML605
37 default 0x38000000 if XTFPGA_KC705
/openbmc/u-boot/board/altera/arria5-socdk/qts/
H A Diocsr_config.h15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000000,
19 0x00000000,
20 0x00008000,
21 0x00060180,
22 0x18060000,
23 0x18000060,
24 0x00018060,
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dof_device_64.c28 ret = 0; in of_ioremap()
53 return 0; in of_bus_pci_match()
62 return 0; in of_bus_pci_match()
67 return 0; in of_bus_pci_match()
85 return 0; in of_bus_simba_match()
91 return 0; in of_bus_simba_map()
110 if (!((addr[0] ^ range[0]) & 0x03000000)) in of_bus_pci_map()
116 if ((addr[0] & 0x03000000) == 0x03000000 && in of_bus_pci_map()
117 (range[0] & 0x03000000) == 0x02000000) in of_bus_pci_map()
131 for (i = 0; i < na - 1; i++) in of_bus_pci_map()
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5272.h20 #define GPIO_PACNT_PA15MSK (0xC0000000)
21 #define GPIO_PACNT_DGNT1 (0x40000000)
22 #define GPIO_PACNT_PA14MSK (0x30000000)
23 #define GPIO_PACNT_DREQ1 (0x10000000)
24 #define GPIO_PACNT_PA13MSK (0x0C000000)
25 #define GPIO_PACNT_DFSC3 (0x04000000)
26 #define GPIO_PACNT_PA12MSK (0x03000000)
27 #define GPIO_PACNT_DFSC2 (0x01000000)
28 #define GPIO_PACNT_PA11MSK (0x00C00000)
29 #define GPIO_PACNT_QSPI_CS1 (0x00800000)
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00080000>;
77 reg = <0x07f80000 0x00080000>;
[all …]
H A Dp1022ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
51 reg = <0x03000000 0x00e00000>;
57 reg = <0x03e00000 0x00200000>;
63 reg = <0x04000000 0x00400000>;
69 reg = <0x04400000 0x03b00000>;
74 reg = <0x07f00000 0x00080000>;
80 reg = <0x07f80000 0x00080000>;
[all …]
H A Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_pick_ph.c9 rs = 0x12345678; in main()
10 rt = 0x87654321; in main()
11 dsp = 0x0A000000; in main()
12 result = 0x12344321; in main()
15 ("wrdsp %3, 0x10\n\t" in main()
16 "pick.ph %0, %1, %2\n\t" in main()
22 rs = 0x12345678; in main()
23 rt = 0x87654321; in main()
24 dsp = 0x03000000; in main()
25 result = 0x12345678; in main()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun50i_h6.h11 #define SUNXI_SRAM_C_BASE 0x00028000
12 #define SUNXI_SRAM_A2_BASE 0x00100000
14 #define SUNXI_DE3_BASE 0x01000000
15 #define SUNXI_SS_BASE 0x01904000
16 #define SUNXI_EMCE_BASE 0x01905000
18 #define SUNXI_SRAMC_BASE 0x03000000
19 #define SUNXI_CCM_BASE 0x03001000
20 #define SUNXI_DMA_BASE 0x03002000
21 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
22 #define SUNXI_SIDC_BASE 0x03006000
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/openbmc/qemu/include/sysemu/
H A Ddevice_tree.h84 * array of strings to a sequential string with \0 separators before
129 for (unsigned i_ = 0; i_ < ARRAY_SIZE(qdt_tmp); i_++) { \
134 } while (0)
163 * Return value: 0 on success, <0 on error.
186 * Return value: 0 on success, <0 on error.
206 #define FDT_PCI_RANGE_RELOCATABLE 0x80000000
207 #define FDT_PCI_RANGE_PREFETCHABLE 0x40000000
208 #define FDT_PCI_RANGE_ALIASED 0x20000000
209 #define FDT_PCI_RANGE_TYPE_MASK 0x03000000
210 #define FDT_PCI_RANGE_MMIO_64BIT 0x03000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun9i-a80-de-clks.yaml59 reg = <0x03000000 0x30>;
H A Dqcom,sc7280-lpasscc.yaml65 reg = <0x03000000 0x40>, <0x03c04000 0x4>;
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588.dtsi12 reg = <0x0 0xfd5b8000 0x0 0x10000>;
17 reg = <0x0 0xfd5c0000 0x0 0x100>;
22 reg = <0x0 0xfddc8000 0x0 0x1000>;
23 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
33 #sound-dai-cells = <0>;
39 reg = <0x0 0xfddf4000 0x0 0x1000>;
40 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
50 #sound-dai-cells = <0>;
56 reg = <0x0 0xfddf8000 0x0 0x1000>;
57 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c45 return nvkm_rd32(device, 0x004600); in read_div()
52 u32 ctrl = nvkm_rd32(device, base + 0); in read_pll()
55 u32 post_div = 0; in read_pll()
56 u32 clock = 0; in read_pll()
60 case 0x4020: in read_pll()
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
63 case 0x4028: in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
[all …]
/openbmc/linux/include/linux/mtd/
H A Dndfc.h12 #define NDFC_CMD 0x00
13 #define NDFC_ALE 0x04
14 #define NDFC_DATA 0x08
15 #define NDFC_ECC 0x10
16 #define NDFC_BCFG0 0x30
17 #define NDFC_BCFG1 0x34
18 #define NDFC_BCFG2 0x38
19 #define NDFC_BCFG3 0x3c
20 #define NDFC_CCR 0x40
21 #define NDFC_STAT 0x44
[all …]
/openbmc/u-boot/include/linux/mtd/
H A Dndfc.h18 #define NDFC_CMD 0x00
19 #define NDFC_ALE 0x04
20 #define NDFC_DATA 0x08
21 #define NDFC_ECC 0x10
22 #define NDFC_BCFG0 0x30
23 #define NDFC_BCFG1 0x34
24 #define NDFC_BCFG2 0x38
25 #define NDFC_BCFG3 0x3c
26 #define NDFC_CCR 0x40
27 #define NDFC_STAT 0x44
[all …]
/openbmc/linux/drivers/net/ethernet/ibm/emac/
H A Dtah.h52 #define TAH_MR_CVR 0x80000000
53 #define TAH_MR_SR 0x40000000
54 #define TAH_MR_ST_256 0x01000000
55 #define TAH_MR_ST_512 0x02000000
56 #define TAH_MR_ST_768 0x03000000
57 #define TAH_MR_ST_1024 0x04000000
58 #define TAH_MR_ST_1280 0x05000000
59 #define TAH_MR_ST_1536 0x06000000
60 #define TAH_MR_TFS_16KB 0x00000000
61 #define TAH_MR_TFS_2KB 0x00200000
[all …]

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