Lines Matching +full:0 +full:x03000000
11 #define SUNXI_SRAM_C_BASE 0x00028000
12 #define SUNXI_SRAM_A2_BASE 0x00100000
14 #define SUNXI_DE3_BASE 0x01000000
15 #define SUNXI_SS_BASE 0x01904000
16 #define SUNXI_EMCE_BASE 0x01905000
18 #define SUNXI_SRAMC_BASE 0x03000000
19 #define SUNXI_CCM_BASE 0x03001000
20 #define SUNXI_DMA_BASE 0x03002000
21 /* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
22 #define SUNXI_SIDC_BASE 0x03006000
23 #define SUNXI_SID_BASE 0x03006200
24 #define SUNXI_TIMER_BASE 0x03009000
25 #define SUNXI_PIO_BASE 0x0300B000
26 #define SUNXI_PSI_BASE 0x0300C000
28 #define SUNXI_GIC400_BASE 0x03020000
29 #define SUNXI_IOMMU_BASE 0x030F0000
31 #define SUNXI_DRAM_COM_BASE 0x04002000
32 #define SUNXI_DRAM_CTL0_BASE 0x04003000
33 #define SUNXI_DRAM_PHY0_BASE 0x04005000
34 #define SUNXI_NFC_BASE 0x04011000
35 #define SUNXI_MMC0_BASE 0x04020000
36 #define SUNXI_MMC1_BASE 0x04021000
37 #define SUNXI_MMC2_BASE 0x04022000
39 #define SUNXI_UART0_BASE 0x05000000
40 #define SUNXI_UART1_BASE 0x05000400
41 #define SUNXI_UART2_BASE 0x05000800
42 #define SUNXI_UART3_BASE 0x05000C00
43 #define SUNXI_TWI0_BASE 0x05002000
44 #define SUNXI_TWI1_BASE 0x05002400
45 #define SUNXI_TWI2_BASE 0x05002800
46 #define SUNXI_TWI3_BASE 0x05002C00
47 #define SUNXI_SPI0_BASE 0x05010000
48 #define SUNXI_SPI1_BASE 0x05011000
49 #define SUNXI_GMAC_BASE 0x05020000
50 #define SUNXI_USB0_BASE 0x05100000
51 #define SUNXI_XHCI_BASE 0x05200000
52 #define SUNXI_USB3_BASE 0x05311000
53 #define SUNXI_PCIE_BASE 0x05400000
55 #define SUNXI_HDMI_BASE 0x06000000
56 #define SUNXI_TCON_TOP_BASE 0x06510000
57 #define SUNXI_TCON_LCD0_BASE 0x06511000
58 #define SUNXI_TCON_TV0_BASE 0x06515000
60 #define SUNXI_RTC_BASE 0x07000000
61 #define SUNXI_R_CPUCFG_BASE 0x07000400
62 #define SUNXI_PRCM_BASE 0x07010000
63 #define SUNXI_R_PIO_BASE 0x07022000
64 #define SUNXI_R_UART_BASE 0x07080000
65 #define SUNXI_R_TWI_BASE 0x07081400