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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dbosch,m_can.yaml66 0x0 if you're using a private Message RAM. The remain cells
70 11-bit Filter 0-128 elements / 0-128 words
71 29-bit Filter 0-64 elements / 0-128 words
72 Rx FIFO 0 0-64 elements / 0-1152 words
73 Rx FIFO 1 0-64 elements / 0-1152 words
74 Rx Buffers 0-64 elements / 0-1152 words
75 Tx Event FIFO 0-32 elements / 0-64 words
76 Tx Buffers 0-32 elements / 0-576 words
83 the following elements start from. This is usually set to 0x0 if
85 default: 0
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx6ul.h97 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
116 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
120 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
121 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
[all …]
H A Dfsl-imx6.h84 #define FSL_IMX6_MMDC_ADDR 0x10000000
85 #define FSL_IMX6_MMDC_SIZE 0xF0000000
86 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
87 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
88 #define FSL_IMX6_IPU_2_ADDR 0x02800000
89 #define FSL_IMX6_IPU_2_SIZE 0x400000
90 #define FSL_IMX6_IPU_1_ADDR 0x02400000
91 #define FSL_IMX6_IPU_1_SIZE 0x400000
92 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
93 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sll.dtsi44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
85 reg = <0x00a01000 0x1000>,
86 <0x00a00100 0x100>;
92 #size-cells = <0>;
94 ckil: clock@0 {
96 reg = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
[all …]
H A Dimx6ul.dtsi55 #size-cells = <0>;
57 cpu0: cpu@0 {
60 reg = <0>;
98 reg = <0x00a01000 0x1000>,
99 <0x00a02000 0x1000>,
100 <0x00a04000 0x2000>,
101 <0x00a06000 0x2000>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
120 #clock-cells = <0>;
[all …]
H A Dimx6sl.dtsi24 memory { device_type = "memory"; reg = <0 0>; };
48 #size-cells = <0>;
50 cpu@0 {
53 reg = <0x0>;
83 reg = <0x00a01000 0x1000>,
84 <0x00a00100 0x100>;
90 #size-cells = <0>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
114 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6qdl.dtsi56 #clock-cells = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
84 #size-cells = <0>;
89 lvds-channel@0 {
91 #size-cells = <0>;
92 reg = <0>;
95 port@0 {
[all …]
H A Dimx6ull.dtsi53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0>;
90 reg = <0x00a01000 0x1000>,
91 <0x00a02000 0x100>;
96 #size-cells = <0>;
98 ckil: clock@0 {
100 reg = <0>;
101 #clock-cells = <0>;
109 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll.dtsi47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
97 clock-frequency = <0>;
103 #clock-cells = <0>;
104 clock-frequency = <0>;
117 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6sl.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
86 #clock-cells = <0>;
92 #clock-cells = <0>;
100 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
105 #phy-cells = <0>;
117 reg = <0x00900000 0x20000>;
118 ranges = <0 0x00900000 0x20000>;
128 reg = <0x00a01000 0x1000>,
[all …]
H A Dimx6ul.dtsi58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
129 #clock-cells = <0>;
130 clock-frequency = <0>;
149 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all …]