Lines Matching +full:0 +full:x020e8000
56 #clock-cells = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
84 #size-cells = <0>;
89 lvds-channel@0 {
91 #size-cells = <0>;
92 reg = <0>;
95 port@0 {
96 reg = <0>;
114 #size-cells = <0>;
118 port@0 {
119 reg = <0>;
139 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
151 reg = <0x00110000 0x2000>;
152 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
153 <0 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>;
166 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
168 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
177 dmas = <&dma_apbh 0>;
184 #size-cells = <0>;
185 reg = <0x00120000 0x9000>;
186 interrupts = <0 115 0x04>;
193 port@0 {
194 reg = <0>;
212 reg = <0x00130000 0x4000>;
213 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
223 reg = <0x00134000 0x4000>;
224 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
233 reg = <0x00a00600 0x20>;
234 interrupts = <1 13 0xf01>;
243 reg = <0x00a01000 0x1000>,
244 <0x00a00100 0x100>;
250 reg = <0x00a02000 0x1000>;
251 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
261 reg = <0x01ffc000 0x04000>,
262 <0x01f00000 0x80000>;
267 bus-range = <0x00 0xff>;
268 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
269 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
274 interrupt-map-mask = <0 0 0 0x7>;
275 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
276 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
277 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
278 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
290 reg = <0x02000000 0x100000>;
297 reg = <0x02000000 0x40000>;
302 reg = <0x02004000 0x4000>;
303 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
304 dmas = <&sdma 14 18 0>,
305 <&sdma 15 18 0>;
322 #size-cells = <0>;
324 reg = <0x02008000 0x4000>;
325 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
336 #size-cells = <0>;
338 reg = <0x0200c000 0x4000>;
339 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
350 #size-cells = <0>;
352 reg = <0x02010000 0x4000>;
353 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
364 #size-cells = <0>;
366 reg = <0x02014000 0x4000>;
367 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
378 reg = <0x02020000 0x4000>;
379 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
383 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
389 #sound-dai-cells = <0>;
391 reg = <0x02024000 0x4000>;
392 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
399 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
405 #sound-dai-cells = <0>;
408 reg = <0x02028000 0x4000>;
409 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
413 dmas = <&sdma 37 1 0>,
414 <&sdma 38 1 0>;
421 #sound-dai-cells = <0>;
424 reg = <0x0202c000 0x4000>;
425 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
429 dmas = <&sdma 41 1 0>,
430 <&sdma 42 1 0>;
437 #sound-dai-cells = <0>;
440 reg = <0x02030000 0x4000>;
441 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
445 dmas = <&sdma 45 1 0>,
446 <&sdma 46 1 0>;
454 reg = <0x02034000 0x4000>;
455 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
457 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
458 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
459 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
460 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
461 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
478 reg = <0x0203c000 0x4000>;
484 reg = <0x02040000 0x3c000>;
485 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
486 <0 3 IRQ_TYPE_LEVEL_HIGH>;
497 reg = <0x0207c000 0x4000>;
503 reg = <0x02080000 0x4000>;
504 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
514 reg = <0x02084000 0x4000>;
515 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
525 reg = <0x02088000 0x4000>;
526 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
536 reg = <0x0208c000 0x4000>;
537 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
546 reg = <0x02090000 0x4000>;
547 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
556 reg = <0x02094000 0x4000>;
557 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
566 reg = <0x02098000 0x4000>;
567 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
576 reg = <0x0209c000 0x4000>;
577 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
578 <0 67 IRQ_TYPE_LEVEL_HIGH>;
587 reg = <0x020a0000 0x4000>;
588 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
589 <0 69 IRQ_TYPE_LEVEL_HIGH>;
598 reg = <0x020a4000 0x4000>;
599 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
600 <0 71 IRQ_TYPE_LEVEL_HIGH>;
609 reg = <0x020a8000 0x4000>;
610 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
611 <0 73 IRQ_TYPE_LEVEL_HIGH>;
620 reg = <0x020ac000 0x4000>;
621 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
622 <0 75 IRQ_TYPE_LEVEL_HIGH>;
631 reg = <0x020b0000 0x4000>;
632 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
633 <0 77 IRQ_TYPE_LEVEL_HIGH>;
642 reg = <0x020b4000 0x4000>;
643 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
644 <0 79 IRQ_TYPE_LEVEL_HIGH>;
653 reg = <0x020b8000 0x4000>;
654 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
661 reg = <0x020bc000 0x4000>;
662 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
668 reg = <0x020c0000 0x4000>;
669 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
676 reg = <0x020c4000 0x4000>;
677 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
678 <0 88 IRQ_TYPE_LEVEL_HIGH>;
684 reg = <0x020c8000 0x1000>;
685 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
686 <0 54 IRQ_TYPE_LEVEL_HIGH>,
687 <0 127 IRQ_TYPE_LEVEL_HIGH>;
695 anatop-reg-offset = <0x110>;
701 anatop-enable-bit = <0>;
710 anatop-reg-offset = <0x120>;
713 anatop-min-bit-val = <0>;
716 anatop-enable-bit = <0>;
725 anatop-reg-offset = <0x130>;
728 anatop-min-bit-val = <0>;
731 anatop-enable-bit = <0>;
740 anatop-reg-offset = <0x140>;
741 anatop-vol-bit-shift = <0>;
743 anatop-delay-reg-offset = <0x170>;
757 anatop-reg-offset = <0x140>;
760 anatop-delay-reg-offset = <0x170>;
774 anatop-reg-offset = <0x140>;
777 anatop-delay-reg-offset = <0x170>;
788 reg = <0x020c9000 0x1000>;
789 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
796 reg = <0x020ca000 0x1000>;
797 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
803 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
804 reg = <0x020cc000 0x4000>;
807 compatible = "fsl,sec-v4.0-mon-rtc-lp";
809 offset = <0x34>;
810 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
811 <0 20 IRQ_TYPE_LEVEL_HIGH>;
817 offset = <0x38>;
818 value = <0x60>;
819 mask = <0x60>;
829 reg = <0x020d0000 0x4000>;
830 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
834 reg = <0x020d4000 0x4000>;
835 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
840 reg = <0x020d8000 0x4000>;
841 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
842 <0 96 IRQ_TYPE_LEVEL_HIGH>;
848 reg = <0x020dc000 0x4000>;
851 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
852 <0 90 IRQ_TYPE_LEVEL_HIGH>;
859 #size-cells = <0>;
861 power-domain@0 {
862 reg = <0>;
863 #power-domain-cells = <0>;
867 #power-domain-cells = <0>;
881 reg = <0x20e0000 0x38>;
891 reg = <0x20e0000 0x4000>;
895 reg = <0x020e4000 0x4000>;
896 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
900 reg = <0x020e8000 0x4000>;
901 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
906 reg = <0x020ec000 0x4000>;
907 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
920 reg = <0x02100000 0x100000>;
924 compatible = "fsl,sec-v4.0";
927 reg = <0x2100000 0x10000>;
928 ranges = <0 0x2100000 0x10000>;
936 compatible = "fsl,sec-v4.0-job-ring";
937 reg = <0x1000 0x1000>;
942 compatible = "fsl,sec-v4.0-job-ring";
943 reg = <0x2000 0x1000>;
949 reg = <0x0217c000 0x4000>;
954 reg = <0x02184000 0x200>;
955 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
958 fsl,usbmisc = <&usbmisc 0>;
959 ahb-burst-config = <0x0>;
960 tx-burst-size-dword = <0x10>;
961 rx-burst-size-dword = <0x10>;
967 reg = <0x02184200 0x200>;
968 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
973 ahb-burst-config = <0x0>;
974 tx-burst-size-dword = <0x10>;
975 rx-burst-size-dword = <0x10>;
981 reg = <0x02184400 0x200>;
982 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
986 ahb-burst-config = <0x0>;
987 tx-burst-size-dword = <0x10>;
988 rx-burst-size-dword = <0x10>;
994 reg = <0x02184600 0x200>;
995 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
999 ahb-burst-config = <0x0>;
1000 tx-burst-size-dword = <0x10>;
1001 rx-burst-size-dword = <0x10>;
1008 reg = <0x02184800 0x200>;
1014 reg = <0x02188000 0x4000>;
1017 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1018 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1027 reg = <0x0218c000 0x4000>;
1028 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1029 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1030 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1035 reg = <0x02190000 0x4000>;
1036 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1047 reg = <0x02194000 0x4000>;
1048 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1059 reg = <0x02198000 0x4000>;
1060 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1071 reg = <0x0219c000 0x4000>;
1072 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1083 #size-cells = <0>;
1085 reg = <0x021a0000 0x4000>;
1086 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1093 #size-cells = <0>;
1095 reg = <0x021a4000 0x4000>;
1096 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1103 #size-cells = <0>;
1105 reg = <0x021a8000 0x4000>;
1106 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1112 reg = <0x021ac000 0x4000>;
1117 reg = <0x021b0000 0x4000>;
1121 reg = <0x021b4000 0x4000>;
1128 reg = <0x021b8000 0x4000>;
1129 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1137 reg = <0x021bc000 0x4000>;
1142 reg = <0x021d0000 0x4000>;
1143 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1147 reg = <0x021d4000 0x4000>;
1148 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1153 reg = <0x021d8000 0x4000>;
1159 reg = <0x021dc000 0x4000>;
1161 #size-cells = <0>;
1162 interrupts = <0 100 0x04>, <0 101 0x04>;
1171 reg = <0x021e0000 0x4000>;
1176 #size-cells = <0>;
1178 port@0 {
1179 reg = <0>;
1198 reg = <0x021e4000 0x4000>;
1199 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1205 reg = <0x021e8000 0x4000>;
1206 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1210 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1217 reg = <0x021ec000 0x4000>;
1218 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1222 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1229 reg = <0x021f0000 0x4000>;
1230 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1234 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1241 reg = <0x021f4000 0x4000>;
1242 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1246 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1254 #size-cells = <0>;
1256 reg = <0x02400000 0x400000>;
1257 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1258 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1265 ipu1_csi0: port@0 {
1266 reg = <0>;
1279 #size-cells = <0>;
1282 ipu1_di0_disp0: endpoint@0 {
1283 reg = <0>;
1309 #size-cells = <0>;
1312 ipu1_di1_disp1: endpoint@0 {
1313 reg = <0>;