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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,suniv-f1c100s-usb-phy.yaml75 reg = <0x01c13400 0x10>;
H A Dallwinner,sun5i-a13-usb-phy.yaml85 reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
H A Dallwinner,sun8i-r40-usb-phy.yaml37 - description: USB Host 0 PHY bus clock
99 reg = <0x01c13400 0x14>,
100 <0x01c14800 0x4>,
101 <0x01c19800 0x4>,
102 <0x01c1c800 0x4>;
H A Dallwinner,sun4i-a10-usb-phy.yaml94 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dsun4i-usb-phy.txt52 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
56 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
59 pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsuniv-f1c100s.dtsi17 #clock-cells = <0>;
24 #clock-cells = <0>;
33 #size-cells = <0>;
35 cpu@0 {
38 reg = <0x0>;
51 reg = <0x01c00000 0x30>;
58 reg = <0x00010000 0x1000>;
61 ranges = <0 0x00010000 0x1000>;
63 otg_sram: sram-section@0 {
66 reg = <0x0000 0x1000>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
97 #clock-cells = <0>;
104 #clock-cells = <0>;
119 size = <0x6000000>;
120 alloc-ranges = <0x40000000 0x10000000>;
135 reg = <0x01c00000 0x30>;
140 sram_a: sram@0 {
142 reg = <0x00000000 0xc000>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
166 #clock-cells = <0>;
173 #clock-cells = <0>;
199 size = <0x6000000>;
200 alloc-ranges = <0x40000000 0x10000000>;
214 reg = <0x01c00000 0x30>;
219 sram_a: sram@0 {
221 reg = <0x00000000 0xc000>;
[all …]
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all …]
H A Dsun7i-a20.dtsi101 #size-cells = <0>;
103 cpu0: cpu@0 {
106 reg = <0>;
181 size = <0x6000000>;
182 alloc-ranges = <0x40000000 0x10000000>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
231 #clock-cells = <0>;
238 #clock-cells = <0>;
245 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-r40.dtsi59 #clock-cells = <0>;
66 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu@0 {
80 reg = <0>;
112 reg = <0x01c00030 0x0c>;
113 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
119 reg = <0x01c0f000 0x1000>;
124 pinctrl-0 = <&mmc0_pins>;
129 #size-cells = <0>;
[all …]
H A Dsun5i.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
71 framebuffer@0 {
97 #clock-cells = <0>;
103 osc32k: clk@0 {
104 #clock-cells = <0>;
119 reg = <0x01c00000 0x30>;
124 sram_a: sram@0 {
126 reg = <0x00000000 0xc000>;
[all …]
H A Dsun4i-a10.dtsi111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
195 reg = <0x01c00000 0x30>;
200 sram_a: sram@0 {
202 reg = <0x00000000 0xc000>;
205 ranges = <0 0x00000000 0xc000>;
209 reg = <0x8000 0x4000>;
[all …]
H A Dsun7i-a20.dtsi65 framebuffer@0 {
100 #size-cells = <0>;
102 cpu0: cpu@0 {
105 reg = <0>;
161 reg = <0x40000000 0x80000000>;
184 #clock-cells = <0>;
190 osc32k: clk@0 {
191 #clock-cells = <0>;
207 #clock-cells = <0>;
214 #clock-cells = <0>;
[all …]