Lines Matching +full:0 +full:x01c13400
111 #size-cells = <0>;
112 cpu0: cpu@0 {
115 reg = <0x0>;
167 #clock-cells = <0>;
174 #clock-cells = <0>;
195 reg = <0x01c00000 0x30>;
200 sram_a: sram@0 {
202 reg = <0x00000000 0xc000>;
205 ranges = <0 0x00000000 0xc000>;
209 reg = <0x8000 0x4000>;
216 reg = <0x00010000 0x1000>;
219 ranges = <0 0x00010000 0x1000>;
221 otg_sram: sram-section@0 {
223 reg = <0x0000 0x1000>;
231 reg = <0x01c02000 0x1000>;
239 reg = <0x01c03000 0x1000>;
247 #size-cells = <0>;
252 reg = <0x01c05000 0x1000>;
261 #size-cells = <0>;
266 reg = <0x01c06000 0x1000>;
274 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
277 #size-cells = <0>;
282 reg = <0x01c0b000 0x1000>;
287 pinctrl-0 = <&emac_pins>;
293 reg = <0x01c0b080 0x14>;
296 #size-cells = <0>;
301 reg = <0x01c0c000 0x1000>;
316 #size-cells = <0>;
318 tcon0_in: port@0 {
320 #size-cells = <0>;
321 reg = <0>;
323 tcon0_in_be0: endpoint@0 {
324 reg = <0>;
336 #size-cells = <0>;
350 reg = <0x01c0d000 0x1000>;
365 #size-cells = <0>;
367 tcon1_in: port@0 {
369 #size-cells = <0>;
370 reg = <0>;
372 tcon1_in_be0: endpoint@0 {
373 reg = <0>;
385 #size-cells = <0>;
399 reg = <0x01c0f000 0x1000>;
404 pinctrl-0 = <&mmc0_pins>;
407 #size-cells = <0>;
412 reg = <0x01c10000 0x1000>;
418 #size-cells = <0>;
423 reg = <0x01c11000 0x1000>;
429 #size-cells = <0>;
434 reg = <0x01c12000 0x1000>;
440 #size-cells = <0>;
445 reg = <0x01c13000 0x0400>;
449 phys = <&usbphy 0>;
451 extcon = <&usbphy 0>;
459 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
472 reg = <0x01c14000 0x100>;
482 reg = <0x01c14400 0x100>;
492 reg = <0x01c15000 0x1000>;
500 reg = <0x01c16000 0x1000>;
505 clock-names = "ahb", "mod", "pll-0", "pll-1";
514 #size-cells = <0>;
516 hdmi_in: port@0 {
518 #size-cells = <0>;
519 reg = <0>;
521 hdmi_in_tcon0: endpoint@0 {
522 reg = <0>;
534 #size-cells = <0>;
542 reg = <0x01c17000 0x1000>;
551 #size-cells = <0>;
556 reg = <0x01c18000 0x1000>;
564 reg = <0x01c1c000 0x100>;
574 reg = <0x01c1c400 0x100>;
584 reg = <0x01c1f000 0x1000>;
593 #size-cells = <0>;
598 reg = <0x01c20000 0x400>;
607 reg = <0x01c20400 0x400>;
614 reg = <0x01c20800 0x400>;
764 reg = <0x01c20c00 0x90>;
771 reg = <0x01c20c90 0x10>;
776 reg = <0x01c20d00 0x20>;
782 reg = <0x01c20e00 0xc>;
789 #sound-dai-cells = <0>;
791 reg = <0x01c21000 0x400>;
806 reg = <0x01c21800 0x40>;
815 reg = <0x01c21c00 0x40>;
820 #sound-dai-cells = <0>;
822 reg = <0x01c22400 0x400>;
834 reg = <0x01c22800 0x100>;
840 #sound-dai-cells = <0>;
842 reg = <0x01c22c00 0x40>;
854 reg = <0x01c23800 0x10>;
859 reg = <0x01c25000 0x100>;
861 #thermal-sensor-cells = <0>;
866 reg = <0x01c28000 0x400>;
876 reg = <0x01c28400 0x400>;
886 reg = <0x01c28800 0x400>;
896 reg = <0x01c28c00 0x400>;
906 reg = <0x01c29000 0x400>;
916 reg = <0x01c29400 0x400>;
926 reg = <0x01c29800 0x400>;
936 reg = <0x01c29c00 0x400>;
946 reg = <0x01c2a000 0x400>;
954 reg = <0x01c2a400 0x400>;
962 reg = <0x01c2ac00 0x400>;
966 pinctrl-0 = <&i2c0_pins>;
969 #size-cells = <0>;
974 reg = <0x01c2b000 0x400>;
978 pinctrl-0 = <&i2c1_pins>;
981 #size-cells = <0>;
986 reg = <0x01c2b400 0x400>;
990 pinctrl-0 = <&i2c2_pins>;
993 #size-cells = <0>;
998 reg = <0x01c2bc00 0x400>;
1006 reg = <0x01e00000 0x20000>;
1016 #size-cells = <0>;
1020 #size-cells = <0>;
1023 fe0_out_be0: endpoint@0 {
1024 reg = <0>;
1038 reg = <0x01e20000 0x20000>;
1048 #size-cells = <0>;
1052 #size-cells = <0>;
1055 fe1_out_be0: endpoint@0 {
1056 reg = <0>;
1070 reg = <0x01e40000 0x10000>;
1080 #size-cells = <0>;
1082 be1_in: port@0 {
1084 #size-cells = <0>;
1085 reg = <0>;
1087 be1_in_fe0: endpoint@0 {
1088 reg = <0>;
1100 #size-cells = <0>;
1103 be1_out_tcon0: endpoint@0 {
1104 reg = <0>;
1118 reg = <0x01e60000 0x10000>;
1128 #size-cells = <0>;
1130 be0_in: port@0 {
1132 #size-cells = <0>;
1133 reg = <0>;
1135 be0_in_fe0: endpoint@0 {
1136 reg = <0>;
1148 #size-cells = <0>;
1151 be0_out_tcon0: endpoint@0 {
1152 reg = <0>;