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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp-pinfunc.h15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
H A Dimx6ul-pinfunc.h13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/openbmc/linux/drivers/usb/storage/
H A Drealtek_cr.c42 MODULE_PARM_DESC(auto_delink_en, "auto delink mode (0=firmware, 1=software [default])");
115 #define FLIDX_AUTO_DELINK 0x01
131 #define VENDOR_ID(chip) ((chip)->status[0].vid)
132 #define PRODUCT_ID(chip) ((chip)->status[0].pid)
133 #define FW_VERSION(chip) ((chip)->status[0].fw_ver)
136 #define STATUS_SUCCESS 0
141 CHK_BIT((chip)->status[0].function[0], 1)
143 CHK_BIT((chip)->status[0].function[0], 2)
145 CHK_BIT((chip)->status[0].function[0], 3)
147 CHK_BIT((chip)->status[0].function[0], 4)
[all …]
H A Dunusual_realtek.h15 UNUSUAL_DEV(0x0bda, 0x0138, 0x0000, 0x9999,
18 USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
20 UNUSUAL_DEV(0x0bda, 0x0153, 0x0000, 0x9999,
23 USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
25 UNUSUAL_DEV(0x0bda, 0x0158, 0x0000, 0x9999,
28 USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
30 UNUSUAL_DEV(0x0bda, 0x0159, 0x0000, 0x9999,
33 USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
35 UNUSUAL_DEV(0x0bda, 0x0177, 0x0000, 0x9999,
38 USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dmx7ulp-pins.h12 …_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000,…
13 … = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000,…
14 …CS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104,…
15 …CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8,…
16 …CL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C,…
17 …IN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8,…
18 …BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8,…
19 … = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000,…
20 …_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000,…
21 … = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000,…
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp-pinfunc.h26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0
27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0
28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0
29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2
30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2
31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2
32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2
33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2
34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0
35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0
[all …]
H A Dimx6ul-pinfunc.h17 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
18 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
24 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
25 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
26 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
27 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
H A Dimx6sll-pinfunc.h17 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
18 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
19 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
20 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
25 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
26 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_4_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dtables_phy_lcn.c30 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
31 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
32 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
33 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
34 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
35 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
36 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
37 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
38 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
39 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx8ulp-pinctrl.yaml73 reg = <0x298c0000 0x10000>;
77 <0x0138 0x08F0 0x4 0x3 0x3>,
78 <0x013C 0x08EC 0x4 0x3 0x3>;
/openbmc/linux/drivers/media/cec/platform/s5p/
H A Dregs-cec.h16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa320.c26 MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
27 MFP_ADDR_X(GPIO5, GPIO9, 0x028C),
28 MFP_ADDR(GPIO10, 0x0458),
29 MFP_ADDR_X(GPIO11, GPIO26, 0x02A0),
30 MFP_ADDR_X(GPIO27, GPIO48, 0x0400),
31 MFP_ADDR_X(GPIO49, GPIO62, 0x045C),
32 MFP_ADDR_X(GPIO63, GPIO73, 0x04B4),
33 MFP_ADDR_X(GPIO74, GPIO98, 0x04F0),
34 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
35 MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674),
[all …]
/openbmc/qemu/target/s390x/
H A Dhelper.c52 vaddr &= 0x7fffffff; in s390_cpu_get_phys_page_debug()
85 return (psw_addr & 0xfffUL) == 0xfffUL; in is_special_wait_psw()
92 if (s390_cpu_halt(cpu) == 0) { in s390_handle_wait()
158 if (env->cregs[10] == 0 && env->cregs[11] == -1LL) { in s390_cpu_recompute_watchpoints()
161 cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL); in s390_cpu_recompute_watchpoints()
167 cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL); in s390_cpu_recompute_watchpoints()
178 uint64_t fprs[16]; /* 0x0000 */
179 uint64_t grs[16]; /* 0x0080 */
180 PSW psw; /* 0x0100 */
181 uint8_t pad_0x0110[0x0118 - 0x0110]; /* 0x0110 */
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_ili9320.c19 #define DEFAULT_GAMMA "07 07 6 0 0 0 5 5 4 0\n" \
20 "07 08 4 7 5 1 2 0 7 7"
24 u8 rxbuf[8] = {0, }; in read_devicecode()
26 write_reg(par, 0x0000); in read_devicecode()
38 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "Device code: 0x%04X\n", in init_display()
40 if ((devcode != 0x0000) && (devcode != 0x9320)) in init_display()
42 "Unrecognized Device code: 0x%04X (expected 0x9320)\n", in init_display()
49 write_reg(par, 0x00E5, 0x8000); in init_display()
52 write_reg(par, 0x0000, 0x0001); in init_display()
55 write_reg(par, 0x0001, 0x0100); in init_display()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Dcpu.h19 u32 tidr; /* 0x00 r */
20 u8 res[0xc];
21 u32 tiocp_cfg; /* 0x10 rw */
22 u32 tistat; /* 0x14 r */
23 u32 tisr; /* 0x18 rw */
24 u32 tier; /* 0x1c rw */
25 u32 twer; /* 0x20 rw */
26 u32 tclr; /* 0x24 rw */
27 u32 tcrr; /* 0x28 rw */
28 u32 tldr; /* 0x2c rw */
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmux.h23 * M0 - Mode 0
28 #define IDIS (0 << 8)
30 #define PTD (0 << 4)
32 #define DIS (0 << 3)
41 #define M0 0
56 #define CONTROL_PADCONF_SDRC_D0 0x0030
57 #define CONTROL_PADCONF_SDRC_D1 0x0032
58 #define CONTROL_PADCONF_SDRC_D2 0x0034
59 #define CONTROL_PADCONF_SDRC_D3 0x0036
60 #define CONTROL_PADCONF_SDRC_D4 0x0038
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dcpu.h23 u32 tidr; /* 0x00 r */
24 u8 res1[0xc];
25 u32 tiocp_cfg; /* 0x10 rw */
26 u8 res2[0x10];
27 u32 tisr_raw; /* 0x24 r */
28 u32 tisr; /* 0x28 rw */
29 u32 tier; /* 0x2c rw */
30 u32 ticr; /* 0x30 rw */
31 u32 twer; /* 0x34 rw */
32 u32 tclr; /* 0x38 rw */
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dsdio.h12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
32 #define MCR_WHISR 0x0010
33 #define MCR_WHIER 0x0014
40 #define WHIER_TX_DONE_INT_EN BIT(0)
47 #define MCR_WASR 0x0020
48 #define MCR_WSICR 0x0024
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dgpio-omap.h18 #define OMAP1_MPUIO_BASE 0xfffb5000
24 #define OMAP_MPUIO_INPUT_LATCH 0x00
25 #define OMAP_MPUIO_OUTPUT 0x04
26 #define OMAP_MPUIO_IO_CNTL 0x08
27 #define OMAP_MPUIO_KBR_LATCH 0x10
28 #define OMAP_MPUIO_KBC 0x14
29 #define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
30 #define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
31 #define OMAP_MPUIO_KBD_INT 0x20
32 #define OMAP_MPUIO_GPIO_INT 0x24
[all …]
/openbmc/linux/sound/firewire/digi00x/
H A Ddigi00x.h63 #define DG00X_ADDR_BASE 0xffffe0000000ull
65 #define DG00X_OFFSET_STREAMING_STATE 0x0000
66 #define DG00X_OFFSET_STREAMING_SET 0x0004
67 /* unknown but address in host space 0x0008 */
68 /* For LSB of the address 0x000c */
69 /* unknown 0x0010 */
70 #define DG00X_OFFSET_MESSAGE_ADDR 0x0014
71 /* For LSB of the address 0x0018 */
72 /* unknown 0x001c */
73 /* unknown 0x0020 */
[all …]

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