Home
last modified time | relevance | path

Searched +full:0 +full:x00ffffff (Results 1 – 25 of 446) sorted by relevance

12345678910>>...18

/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/openbmc/u-boot/drivers/video/
H A Dcfb_console.c144 #define CURSOR_OFF console_cursor(0)
161 #define LINUX_LOGO_LUT_OFFSET 0x20
172 #define VIDEO_LOGO_WIDTH 0
173 #define VIDEO_LOGO_HEIGHT 0
204 #define SWAP16(x) ((((x) & 0x00ff) << 8) | \
207 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | \
208 (((x) & 0x0000ff00) << 8) | \
209 (((x) & 0x00ff0000) >> 8) | \
210 (((x) & 0xff000000) >> 24) \
212 #define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dg364fb.c34 #define G364_MEM_BASE 0xe4400000
35 #define G364_PORT_BASE 0xe4000000
36 #define ID_REG 0xe4000000 /* Read only */
37 #define BOOT_REG 0xe4080000
38 #define TIMING_REG 0xe4080108 /* to 0x080170 - DON'T TOUCH! */
39 #define DISPLAY_REG 0xe4080118
40 #define VDISPLAY_REG 0xe4080150
41 #define MASK_REG 0xe4080200
42 #define CTLA_REG 0xe4080300
43 #define CURS_TOGGLE 0x800000
[all …]
H A Dpxa168fb.h6 /* Video Frame 0&1 start address registers */
7 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
8 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
9 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
10 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
11 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
12 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
13 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
14 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
17 #define LCD_SPU_DMA_PITCH_YC 0x00E0
[all …]
/openbmc/linux/drivers/message/fusion/lsi/
H A Dmpi_fc.h75 #define LINK_SERVICE_BUFFER_POST_FLAGS_PORT_MASK (0x01)
82 U32 NodeNameLow; /* 0Ch */
97 U16 Reserved2; /* 0Ch */
98 U16 IOCStatus; /* 0Eh */
115 #define MPI_LS_BUF_POST_REPLY_FLAG_NO_RSP_NEEDED (0x80)
117 #define MPI_FC_DID_MASK (0x00FFFFFF)
118 #define MPI_FC_DID_SHIFT (0)
119 #define MPI_FC_RCTL_MASK (0xFF000000)
121 #define MPI_FC_SID_MASK (0x00FFFFFF)
122 #define MPI_FC_SID_SHIFT (0)
[all …]
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A Dhardware.h17 #define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */
31 #define VIO_BASE 0xf8000000 /* virtual start of IO space */
33 #define PIO_START 0x80000000 /* physical start of IO space */
36 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
38 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
/openbmc/linux/arch/arm/mach-rpc/include/mach/
H A Duncompress.h37 0x00000000,
38 0x000000cc,
39 0x0000cc00, /* Green */
40 0x0000cccc, /* Yellow */
41 0x00cc0000, /* Blue */
42 0x00cc00cc, /* Magenta */
43 0x00cccc00, /* Cyan */
44 0x00cccccc, /* White */
45 0x00000000,
46 0x000000ff,
[all …]
/openbmc/linux/sound/pci/pcxhr/
H A Dpcxhr_core.h26 #define PCXHR_DSP_TIME_MASK 0x00ffffff
27 #define PCXHR_DSP_TIME_INVALID 0x10000000
47 CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */
51 CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */
52 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
54 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
55 CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */
56 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
57 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
58 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
[all …]
/openbmc/linux/sound/soc/sh/rcar/
H A Dctu.c24 * 0001: Connect input data of channel 0
32 * 1001: Connect calculated data by scale values of matrix row 0
42 * [Output4] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
43 * [Output5] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
44 * [Output6] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
45 * [Output7] = [ 0, 0, 0, 0, 0, 0, 0, 0 ]
53 * H'40_0000 1 0 H'C0_0000 1 0
56 * H'00_0000 0 Mute H'FF_FFFF 2.38 x 10^-7 -132
60 * 1ch -> 0ch
61 * 0ch -> 1ch
[all …]
/openbmc/phosphor-logging/extensions/openpower-pels/
H A Dlog_id.cpp34 constexpr uint32_t bmcLogIDPrefix = 0x50000000;
42 return (id & 0x00FFFFFF) | bmcLogIDPrefix; in addLogIDPrefix()
70 uint32_t id = 0; in generatePELID()
95 if (id == 0x00FFFFFF) in generatePELID()
120 while (ch == '\0') in checkFileForZeroData()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c19 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
20 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
21 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
22 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
23 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
24 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
25 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
26 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
27 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
36 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
[all …]
/openbmc/qemu/ui/
H A Dcursor.c13 unsigned int line = 0, i, r, g, b, x, y, pixel; in cursor_parse_xpm()
31 for (i = 0; i < colors; i++, line++) { in cursor_parse_xpm()
34 ctab[idx] = (0xff << 24) | (b << 16) | (g << 8) | r; in cursor_parse_xpm()
37 if (strcmp(name, "None") == 0) { in cursor_parse_xpm()
38 ctab[idx] = 0x00000000; in cursor_parse_xpm()
51 for (pixel = 0, y = 0; y < height; y++, line++) { in cursor_parse_xpm()
52 for (x = 0; x < height; x++, pixel++) { in cursor_parse_xpm()
66 for (y = 0; y < c->height; y++) { in cursor_print_ascii_art()
68 for (x = 0; x < c->width; x++, data++) { in cursor_print_ascii_art()
69 if ((*data & 0xff000000) != 0xff000000) { in cursor_print_ascii_art()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7m/
H A Dsystick-timer.c30 #define SYSTICK_BASE 0xE000E010
39 #define TIMER_MAX_VAL 0x00FFFFFF
40 #define SYSTICK_CTRL_EN BIT(0)
41 /* Clock source: 0 = Ref clock, 1 = CPU clock */
45 #define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF
62 /* Any write to current_val reg clears it to 0 */ in timer_init()
63 writel(0, &systick->current_val); in timer_init()
83 gd->arch.tbl = 0; in timer_init()
84 gd->arch.tbu = 0; in timer_init()
87 return 0; in timer_init()
/openbmc/linux/drivers/cpufreq/
H A Damd_freq_sensitivity.c25 #define MSR_AMD64_FREQ_SENSITIVITY_ACTUAL 0xc0010080
26 #define MSR_AMD64_FREQ_SENSITIVITY_REFERENCE 0xc0010081
58 actual.h &= 0x00ffffff; in amd_powersave_bias_target()
59 reference.h &= 0x00ffffff; in amd_powersave_bias_target()
70 /* divide by 0, so stay on current frequency as well */ in amd_powersave_bias_target()
71 if (d_reference == 0) { in amd_powersave_bias_target()
79 clamp(sensitivity, 0, POWERSAVE_BIAS_MAX); in amd_powersave_bias_target()
101 data->freq_prev = 0; in amd_powersave_bias_target()
140 return 0; in amd_freq_sensitivity_init()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dregs.h5 #define NV04_PGRAPH_DEBUG_0 0x00400080
6 #define NV04_PGRAPH_DEBUG_1 0x00400084
7 #define NV04_PGRAPH_DEBUG_2 0x00400088
8 #define NV04_PGRAPH_DEBUG_3 0x0040008c
9 #define NV10_PGRAPH_DEBUG_4 0x00400090
10 #define NV03_PGRAPH_INTR 0x00400100
11 #define NV03_PGRAPH_NSTATUS 0x00400104
20 #define NV03_PGRAPH_NSOURCE 0x00400108
21 # define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0)
40 #define NV03_PGRAPH_INTR_EN 0x00400140
[all …]
/openbmc/linux/drivers/infiniband/sw/siw/
H A Dsiw_mem.c23 struct xa_limit limit = XA_LIMIT(1, 0x00ffffff); in siw_mem_add()
27 next &= 0x00ffffff; in siw_mem_add()
30 GFP_KERNEL) < 0) in siw_mem_add()
38 return 0; in siw_mem_add()
74 for (i = 0; num_pages; i++) { in siw_umem_release()
94 struct xa_limit limit = XA_LIMIT(1, 0x00ffffff); in siw_mr_add_mem()
101 mem->stag_valid = 0; in siw_mr_add_mem()
110 next &= 0x00ffffff; in siw_mr_add_mem()
113 GFP_KERNEL) < 0) { in siw_mr_add_mem()
123 return 0; in siw_mr_add_mem()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_led.c44 div = nvif_rd32(device, 0x61c880) & 0x00ffffff; in nouveau_led_get_brightness()
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
47 if (div > 0) in nouveau_led_get_brightness()
50 return 0; in nouveau_led_get_brightness()
72 nvif_wr32(device, 0x61c880, div); in nouveau_led_set_brightness()
73 nvif_wr32(device, 0x61c884, 0xc0000000 | duty); in nouveau_led_set_brightness()
86 return 0; in nouveau_led_init()
89 if (nvkm_gpio_find(gpio, 0, DCB_GPIO_LOGO_LED_PWM, 0xff, &logo_led)) in nouveau_led_init()
90 return 0; in nouveau_led_init()
109 return 0; in nouveau_led_init()
/openbmc/linux/include/soc/fsl/
H A Ddpaa2-global.h47 #define DPAA2_DQ_STAT_FQEMPTY 0x80
49 #define DPAA2_DQ_STAT_HELDACTIVE 0x40
51 #define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
53 #define DPAA2_DQ_STAT_VALIDFRAME 0x10
55 #define DPAA2_DQ_STAT_ODPVALID 0x04
57 #define DPAA2_DQ_STAT_VOLATILE 0x02
59 #define DPAA2_DQ_STAT_EXPIRED 0x01
61 #define DQ_FQID_MASK 0x00FFFFFF
62 #define DQ_FRAME_COUNT_MASK 0x00FFFFFF
78 * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
[all …]
/openbmc/linux/arch/powerpc/sysdev/xics/
H A Dicp-opal.c27 opal_int_set_mfrr(hw_cpu, 0xff); in icp_opal_teardown_cpu()
34 * but want to leave our priority 0. in icp_opal_flush_ipi()
40 if (opal_int_eoi((0x00 << 24) | XICS_IPI) > 0) in icp_opal_flush_ipi()
57 if (rc < 0) in icp_opal_get_xirr()
58 return 0; in icp_opal_get_xirr()
69 vec = xirr & 0x00ffffff; in icp_opal_get_irq()
71 return 0; in icp_opal_get_irq()
83 if (opal_int_eoi(xirr) > 0) in icp_opal_get_irq()
86 return 0; in icp_opal_get_irq()
120 if (rc > 0) in icp_opal_eoi()
[all …]
/openbmc/linux/sound/drivers/vx/
H A Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Dphy.h96 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
121 if (chip->rfe_defs_size == 0) in rtw_get_rfe_def()
141 return 0; in rtw_check_supported_rfe()
168 #define MASKBYTE0 0xff
169 #define MASKBYTE1 0xff00
170 #define MASKBYTE2 0xff0000
171 #define MASKBYTE3 0xff000000
172 #define MASKHWORD 0xffff0000
173 #define MASKLWORD 0x0000ffff
174 #define MASKDWORD 0xffffffff
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h22 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
29 u32 dram_timing4; /* 0x10 */
34 u32 dram_addrw; /* 0x2c */
35 u32 dram_if_width; /* 0x30 */
39 u32 sbe_count; /* 0x40 */
43 u32 drop_addr; /* 0x50 */
47 u32 ctrl_width; /* 0x60 */
51 u32 rfifo_cmap; /* 0x70 */
55 u32 fpgaport_rst; /* 0x80 */
59 u32 prot_rule_addr; /* 0x90 */
[all …]
/openbmc/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/openbmc/linux/include/dt-bindings/mailbox/
H A Dtegra186-hsp.h13 #define TEGRA_HSP_MBOX_TYPE_DB 0x0
14 #define TEGRA_HSP_MBOX_TYPE_SM 0x1
15 #define TEGRA_HSP_MBOX_TYPE_SS 0x2
16 #define TEGRA_HSP_MBOX_TYPE_AS 0x3
34 #define TEGRA_HSP_SM_MASK 0x00ffffff
35 #define TEGRA_HSP_SM_FLAG_RX (0 << 31)
/openbmc/linux/arch/arm/include/debug/
H A Ddc21285.S14 .equ dc21285_high, ARMCSR_BASE & 0xff000000
15 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
21 mov \rp, #0
24 orr \rp, \rp, #0x42000000
28 str \rd, [\rx, #0x160] @ UARTDR
32 1001: ldr \rd, [\rx, #0x178] @ UARTFLG

12345678910>>...18