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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx1-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
31 * the pin number on the specific port (between 0 and 31).
34 #define MX1_PAD_A24__A24 0x00 0x004
35 #define MX1_PAD_A24__GPIO1_0 0x00 0x032
36 #define MX1_PAD_A24__SPI2_CLK 0x00 0x006
[all …]
H A Dimx27-pinfunc.h15 * function: 0 - Primary function
18 * direction: 0 - Input
20 * gpio_oconf: 0 - A_IN
24 * gpio_iconfa/b: 0 - GPIO_IN
26 * 2 - 0
29 * 'pin' is an integer between 0 and 0xbf. imx27 has 6 ports with 32
31 * the pin number on the specific port (between 0 and 31).
34 #define MX27_PAD_USBH2_CLK__USBH2_CLK 0x00 0x000
35 #define MX27_PAD_USBH2_CLK__GPIO1_0 0x00 0x032
36 #define MX27_PAD_USBH2_DIR__USBH2_DIR 0x01 0x000
[all …]
/openbmc/linux/sound/pci/oxygen/
H A Dwm8776.h14 #define WM8776_HPLVOL 0x00
15 #define WM8776_HPRVOL 0x01
16 #define WM8776_HPMASTER 0x02
17 #define WM8776_DACLVOL 0x03
18 #define WM8776_DACRVOL 0x04
19 #define WM8776_DACMASTER 0x05
20 #define WM8776_PHASESWAP 0x06
21 #define WM8776_DACCTRL1 0x07
22 #define WM8776_DACMUTE 0x08
23 #define WM8776_DACCTRL2 0x09
[all …]
H A Dwm8785.h5 #define WM8785_R0 0
11 #define WM8785_MCR_MASK 0x007
12 #define WM8785_MCR_SLAVE 0x000
13 #define WM8785_MCR_MASTER_128 0x001
14 #define WM8785_MCR_MASTER_192 0x002
15 #define WM8785_MCR_MASTER_256 0x003
16 #define WM8785_MCR_MASTER_384 0x004
17 #define WM8785_MCR_MASTER_512 0x005
18 #define WM8785_MCR_MASTER_768 0x006
19 #define WM8785_OSR_MASK 0x018
[all …]
H A Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/openbmc/linux/include/sound/sof/
H A Dheader.h23 * 0xGCCCNNNN where
34 #define SOF_GLB_TYPE_MASK (0xfUL << SOF_GLB_TYPE_SHIFT)
39 #define SOF_CMD_TYPE_MASK (0xfffL << SOF_CMD_TYPE_SHIFT)
43 #define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U)
44 #define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U)
45 #define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U)
46 #define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U)
47 #define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U)
48 #define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U)
49 #define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U)
[all …]
/openbmc/linux/tools/testing/selftests/bpf/verifier/
H A Datomic_fetch.c5 BPF_LD_MAP_FD(BPF_REG_8, 0),
6 BPF_LD_MAP_FD(BPF_REG_9, 0),
9 BPF_STX_MEM(BPF_DW, BPF_REG_2, BPF_REG_9, 0),
10 BPF_ATOMIC_OP(BPF_DW, BPF_AND | BPF_FETCH, BPF_REG_2, BPF_REG_1, 0),
11 BPF_LDX_MEM(BPF_DW, BPF_REG_9, BPF_REG_2, 0),
12 BPF_ST_MEM(BPF_DW, BPF_REG_2, 0, 0),
15 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 1),
16 BPF_STX_MEM(BPF_DW, BPF_REG_0, BPF_REG_9, 0),
17 BPF_MOV64_IMM(BPF_REG_0, 0),
29 BPF_LD_MAP_FD(BPF_REG_8, 0),
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dssm2602.h33 #define SSM2602_LINVOL 0x00
34 #define SSM2602_RINVOL 0x01
35 #define SSM2602_LOUT1V 0x02
36 #define SSM2602_ROUT1V 0x03
37 #define SSM2602_APANA 0x04
38 #define SSM2602_APDIGI 0x05
39 #define SSM2602_PWR 0x06
40 #define SSM2602_IFACE 0x07
41 #define SSM2602_SRATE 0x08
42 #define SSM2602_ACTIVE 0x09
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dsp887x.c38 } while (0)
42 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = len }; in i2c_writebytes()
51 return 0; in i2c_writebytes()
56 u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff }; in sp887x_writereg()
57 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 4 }; in sp887x_writereg()
64 if (!(reg == 0xf1a && data == 0x000 && in sp887x_writereg()
68 __func__, reg & 0xffff, data & 0xffff, ret); in sp887x_writereg()
73 return 0; in sp887x_writereg()
78 u8 b0 [] = { reg >> 8 , reg & 0xff }; in sp887x_readreg()
81 struct i2c_msg msg[] = {{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 2 }, in sp887x_readreg()
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Dintc-525x.c28 imr &= ~(0x001 << irq); in intc2_irq_gpio_mask()
30 imr &= ~(0x100 << irq); in intc2_irq_gpio_mask()
41 imr |= (0x001 << irq); in intc2_irq_gpio_unmask()
43 imr |= (0x100 << irq); in intc2_irq_gpio_unmask()
49 u32 imr = 0; in intc2_irq_gpio_ack()
54 imr |= (0x001 << irq); in intc2_irq_gpio_ack()
56 imr |= (0x100 << irq); in intc2_irq_gpio_ack()
64 return 0; in intc2_irq_gpio_set_type()
88 return 0; in mcf_intc2_init()
/openbmc/linux/drivers/media/i2c/
H A Dsaa717x.c36 MODULE_PARM_DESC(debug, "Debug level (0-1)");
76 #define TUNER_AUDIO_MONO 0 /* LL */
90 int fw_addr = reg == 0x454 || (reg >= 0x464 && reg <= 0x478) || reg == 0x480 || reg == 0x488; in saa717x_write()
94 msg.flags = 0; in saa717x_write()
96 mm1[0] = (reg >> 8) & 0xff; in saa717x_write()
97 mm1[1] = reg & 0xff; in saa717x_write()
100 mm1[4] = (value >> 16) & 0xff; in saa717x_write()
101 mm1[3] = (value >> 8) & 0xff; in saa717x_write()
102 mm1[2] = value & 0xff; in saa717x_write()
104 mm1[2] = value & 0xff; in saa717x_write()
[all …]
/openbmc/linux/drivers/net/ethernet/seeq/
H A Dsgiseeq.h35 #define SEEQ_RSTAT_OVERF 0x001 /* Overflow */
36 #define SEEQ_RSTAT_CERROR 0x002 /* CRC error */
37 #define SEEQ_RSTAT_DERROR 0x004 /* Dribble error */
38 #define SEEQ_RSTAT_SFRAME 0x008 /* Short frame */
39 #define SEEQ_RSTAT_REOF 0x010 /* Received end of frame */
40 #define SEEQ_RSTAT_FIG 0x020 /* Frame is good */
41 #define SEEQ_RSTAT_TIMEO 0x040 /* Timeout, or late receive */
42 #define SEEQ_RSTAT_WHICH 0x080 /* Which status, 1=old 0=new */
43 #define SEEQ_RSTAT_LITTLE 0x100 /* DMA is done in little endian format */
44 #define SEEQ_RSTAT_SDMA 0x200 /* DMA has started */
[all …]
/openbmc/u-boot/board/ti/ti816x/
H A Devm.c28 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
32 return 0; in board_init()
46 mac_addr[0] = mac_hi & 0xFF; in board_eth_init()
47 mac_addr[1] = (mac_hi & 0xFF00) >> 8; in board_eth_init()
48 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; in board_eth_init()
49 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; in board_eth_init()
50 mac_addr[4] = mac_lo & 0xFF; in board_eth_init()
51 mac_addr[5] = (mac_lo & 0xFF00) >> 8; in board_eth_init()
64 { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
65 { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
[all …]
/openbmc/linux/drivers/iommu/intel/
H A Dperfmon.c13 PMU_FORMAT_ATTR(event, "config:0-27"); /* ES: Events Select */
86 return 0; \
87 return (iommu_pmu->filter & _filter) ? attr->mode : 0; \
96 IOMMU_PMU_ATTR(filter_requester_id_en, "config1:0", IOMMU_PMU_FILTER_REQUESTER_ID);
103 IOMMU_PMU_ATTR(filter_pasid, "config2:0-21", IOMMU_PMU_FILTER_PASID);
107 #define iommu_pmu_en_requester_id(e) ((e) & 0x1)
108 #define iommu_pmu_en_domain(e) (((e) >> 1) & 0x1)
109 #define iommu_pmu_en_pasid(e) (((e) >> 2) & 0x1)
110 #define iommu_pmu_en_ats(e) (((e) >> 3) & 0x1)
111 #define iommu_pmu_en_page_table(e) (((e) >> 4) & 0x1)
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_doorbell.h99 AMDGPU_DOORBELL_KIQ = 0x000,
100 AMDGPU_DOORBELL_HIQ = 0x001,
101 AMDGPU_DOORBELL_DIQ = 0x002,
102 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
103 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
104 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
105 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
106 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
107 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
108 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Dcache.h20 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
24 #define ARC_UNCACHED_ADDR_SPACE 0xc0000000
35 " ld.di %0, [%1] \n" \
44 " st.di %0, [%1] \n" \
71 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
72 #define ARC_REG_IC_IVIC 0x10
73 #define ARC_REG_IC_CTRL 0x11
74 #define ARC_REG_IC_IVIR 0x16
75 #define ARC_REG_IC_ENDR 0x17
76 #define ARC_REG_IC_IVIL 0x19
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dddrmphy-regs.h15 #define MPHY_RIDR (0x000 << MPHY_SHIFT)
16 #define MPHY_PIR (0x001 << MPHY_SHIFT)
17 #define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */
33 #define MPHY_PGCR0 (0x002 << MPHY_SHIFT)
35 #define MPHY_PGCR1 (0x003 << MPHY_SHIFT)
37 #define MPHY_PGCR2 (0x004 << MPHY_SHIFT)
40 #define MPHY_PGCR3 (0x005 << MPHY_SHIFT)
41 #define MPHY_PGSR0 (0x006 << MPHY_SHIFT)
42 #define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
62 #define MPHY_PGSR1 (0x007 << MPHY_SHIFT)
[all …]
H A Dddrphy-regs.h14 #define PHY_RIDR (0x000 << PHY_REG_SHIFT)
15 #define PHY_PIR (0x001 << PHY_REG_SHIFT)
16 #define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
34 #define PHY_PGCR0 (0x002 << PHY_REG_SHIFT)
35 #define PHY_PGCR1 (0x003 << PHY_REG_SHIFT)
37 #define PHY_PGSR0 (0x004 << PHY_REG_SHIFT)
38 #define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */
60 #define PHY_PGSR1 (0x005 << PHY_REG_SHIFT)
62 #define PHY_PLLCR (0x006 << PHY_REG_SHIFT)
63 #define PHY_PTR0 (0x007 << PHY_REG_SHIFT)
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
H A Dphy_ac.h7 #define B43_PHY_AC_BBCFG 0x001
8 #define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */
9 #define B43_PHY_AC_BANDCTL 0x003 /* Band control */
10 #define B43_PHY_AC_BANDCTL_5GHZ 0x0001
11 #define B43_PHY_AC_TABLE_ID 0x00d
12 #define B43_PHY_AC_TABLE_OFFSET 0x00e
13 #define B43_PHY_AC_TABLE_DATA1 0x00f
14 #define B43_PHY_AC_TABLE_DATA2 0x010
15 #define B43_PHY_AC_TABLE_DATA3 0x011
16 #define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */
[all …]
/openbmc/linux/arch/mips/math-emu/
H A Ddp_sqrt.c13 0, 1204, 3062, 5746, 9193, 13348, 18162, 23592,
41 /* sqrt(0) = 0 */ in ieee754dp_sqrt()
72 scalx = 0; in ieee754dp_sqrt()
81 x = builddp(0, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); in ieee754dp_sqrt()
86 yh = (yh >> 1) + 0x1ff80000; in ieee754dp_sqrt()
88 y.bits = ((u64) yh << 32) | (y.bits & 0xffffffff); in ieee754dp_sqrt()
91 /* t=x/y; y=y+t; py[n0]=py[n0]-0x00100006; py[n1]=0; */ in ieee754dp_sqrt()
94 y.bits -= 0x0010000600000000LL; in ieee754dp_sqrt()
95 y.bits &= 0xffffffff00000000LL; in ieee754dp_sqrt()
98 /* t=y*y; z=t; pt[n0]+=0x00100000; t+=z; z=(x-z)*y; */ in ieee754dp_sqrt()
[all …]
/openbmc/linux/drivers/hwtracing/coresight/
H A Dcoresight-etm4x-cfg.h16 #define ETM4_CFG_RES_CTR 0x001
17 #define ETM4_CFG_RES_CMP 0x002
18 #define ETM4_CFG_RES_CMP_PAIR0 0x003
19 #define ETM4_CFG_RES_CMP_PAIR1 0x004
20 #define ETM4_CFG_RES_SEL 0x005
21 #define ETM4_CFG_RES_SEL_PAIR0 0x006
22 #define ETM4_CFG_RES_SEL_PAIR1 0x007
23 #define ETM4_CFG_RES_SEQ 0x008
24 #define ETM4_CFG_RES_TS 0x009
25 #define ETM4_CFG_RES_MASK 0x00F
/openbmc/u-boot/arch/microblaze/include/asm/
H A Dmicroblaze_timer.h8 #define TIMER_ENABLE_ALL 0x400 /* ENALL */
9 #define TIMER_PWM 0x200 /* PWMA0 */
10 #define TIMER_INTERRUPT 0x100 /* T0INT */
11 #define TIMER_ENABLE 0x080 /* ENT0 */
12 #define TIMER_ENABLE_INTR 0x040 /* ENIT0 */
13 #define TIMER_RESET 0x020 /* LOAD0 */
14 #define TIMER_RELOAD 0x010 /* ARHT0 */
15 #define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */
16 #define TIMER_EXT_COMPARE 0x004 /* GENT0 */
17 #define TIMER_DOWN_COUNT 0x002 /* UDT0 */
[all …]

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