Lines Matching +full:0 +full:x001

28 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;  in board_init()
32 return 0; in board_init()
46 mac_addr[0] = mac_hi & 0xFF; in board_eth_init()
47 mac_addr[1] = (mac_hi & 0xFF00) >> 8; in board_eth_init()
48 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; in board_eth_init()
49 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; in board_eth_init()
50 mac_addr[4] = mac_lo & 0xFF; in board_eth_init()
51 mac_addr[5] = (mac_lo & 0xFF00) >> 8; in board_eth_init()
64 { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
65 { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
66 { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
67 { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
68 { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
69 { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
70 { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
85 #define EMIF_TIM1 0x1779C9FE
86 #define EMIF_TIM2 0x50608074
87 #define EMIF_TIM3 0x009F857F
88 #define EMIF_SDREF 0x10001841
89 #define EMIF_SDCFG 0x62A73832
90 #define EMIF_PHYCFG 0x00000110
101 .cmd0csratio = 0x100,
102 .cmd0iclkout = 0x001,
103 .cmd1csratio = 0x100,
104 .cmd1iclkout = 0x001,
105 .cmd2csratio = 0x100,
106 .cmd2iclkout = 0x001,
110 #define RD_DQS_GATE (0x1B3)
111 #define RD_DQS (0x35)
112 #define WR_DQS (0x93)
114 .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
115 .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
116 .datawiratio0 = ((0x20<<10) | 0x20<<0),
117 .datagiratio0 = ((0x20<<10) | 0x20<<0),
118 .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
119 .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
123 .dmm_lisa_map_0 = 0x00000000,
124 .dmm_lisa_map_1 = 0x00000000,
125 .dmm_lisa_map_2 = 0x80640300,
126 .dmm_lisa_map_3 = 0xC0640320,