/openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/ |
H A D | ps7_init_gpl.c | 9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d), 10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220), 11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000), 12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010), 13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001), 14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000), 15 EMIT_MASKPOLL(0xf800010c, 0x00000001), 16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000), 17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200), 18 EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220), [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_11_0_0_default.h | 28 #define regSDMA0_DEC_START_DEFAULT 0x00000000 29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000 30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000 31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000 32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000 33 #define regSDMA0_CNTL_DEFAULT 0x00002440 34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186 35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545 36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545 37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 [all …]
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H A D | gc_10_3_0_default.h | 27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000 28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000 29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000 30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000 31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000 32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000 33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000 34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050 35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100 36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2 [all …]
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H A D | gc_10_1_0_default.h | 26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000 27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000 28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000 29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000 30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000 31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050 32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100 33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2 34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107 35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044 [all …]
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H A D | gc_9_0_default.h | 26 #define mmGRBM_CNTL_DEFAULT 0x00000018 27 #define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020 28 #define mmGRBM_STATUS2_DEFAULT 0x00000000 29 #define mmGRBM_PWR_CNTL_DEFAULT 0x00000000 30 #define mmGRBM_STATUS_DEFAULT 0x00000000 31 #define mmGRBM_STATUS_SE0_DEFAULT 0x00000000 32 #define mmGRBM_STATUS_SE1_DEFAULT 0x00000000 33 #define mmGRBM_SOFT_RESET_DEFAULT 0x00000000 34 #define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100 35 #define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008 [all …]
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | pci.c | 50 hose = &pci_hose[0]; in pci_mpc85xx_init() 52 hose->first_busno = 0; in pci_mpc85xx_init() 53 hose->last_busno = 0xff; in pci_mpc85xx_init() 56 (CONFIG_SYS_IMMR+0x8000), in pci_mpc85xx_init() 57 (CONFIG_SYS_IMMR+0x8004)); in pci_mpc85xx_init() 62 dev = PCI_BDF(hose->first_busno, 0, 0); in pci_mpc85xx_init() 70 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); in pci_mpc85xx_init() 82 pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff; in pci_mpc85xx_init() 83 pcix->potear1 = 0x00000000; in pci_mpc85xx_init() 84 pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff; in pci_mpc85xx_init() [all …]
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/openbmc/u-boot/arch/arm/mach-uniphier/clk/ |
H A D | pll-pro4.c | 30 tmp |= 0x00000001; in vpll_init() 33 tmp |= 0x00000001; in vpll_init() 38 tmp &= ~0x10000000; in vpll_init() 41 tmp &= ~0x10000000; in vpll_init() 44 /* Set VPLA_M and VPLB_M to 0x20 */ in vpll_init() 46 tmp &= ~0x0000007f; in vpll_init() 47 tmp |= 0x00000020; in vpll_init() 50 tmp &= ~0x0000007f; in vpll_init() 51 tmp |= 0x00000020; in vpll_init() 58 tmp &= ~0x000fffff; in vpll_init() [all …]
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H A D | pll-ld4.c | 23 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ in upll_init() 25 tmp &= ~0x18000000; in upll_init() 32 tmp &= ~0x07ffffff; in upll_init() 33 tmp |= 0x0228f5c0; in upll_init() 36 tmp &= ~0x07ffffff; in upll_init() 37 tmp |= 0x02328000; in upll_init() 44 tmp |= 0x08000000; in upll_init() 51 tmp |= 0x10000000; in upll_init() 64 tmp |= 0x00000001; in vpll_init() 67 tmp |= 0x00000001; in vpll_init() [all …]
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/openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
H A D | rtw8852b_rfk_table.c | 8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c), 9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0), 10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868), 11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128), 12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b), 13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c), 14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0), 15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868), 16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128), 17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b), [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | uvd_v3_1.c | 46 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit() 47 radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v3_1_semaphore_emit() 49 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit() 50 radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); in uvd_v3_1_semaphore_emit() 52 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit() 53 radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); in uvd_v3_1_semaphore_emit()
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H A D | r600_reg.h | 31 #define R600_PCIE_PORT_INDEX 0x0038 32 #define R600_PCIE_PORT_DATA 0x003c 34 #define R600_RCU_INDEX 0x0100 35 #define R600_RCU_DATA 0x0104 37 #define R600_UVD_CTX_INDEX 0xf4a0 38 #define R600_UVD_CTX_DATA 0xf4a4 40 #define R600_MC_VM_FB_LOCATION 0x2180 41 #define R600_MC_FB_BASE_MASK 0x0000FFFF 42 #define R600_MC_FB_BASE_SHIFT 0 43 #define R600_MC_FB_TOP_MASK 0xFFFF0000 [all …]
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H A D | uvd_v2_2.c | 45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit() 47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v2_2_fence_emit() 51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit() 52 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit() 54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit() 55 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit() 56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit() 57 radeon_ring_write(ring, 0); in uvd_v2_2_fence_emit() [all …]
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/openbmc/linux/drivers/media/platform/ti/vpe/ |
H A D | vpe_regs.h | 16 #define VPE_PID 0x0000 17 #define VPE_PID_MINOR_MASK 0x3f 18 #define VPE_PID_MINOR_SHIFT 0 19 #define VPE_PID_CUSTOM_MASK 0x03 21 #define VPE_PID_MAJOR_MASK 0x07 23 #define VPE_PID_RTL_MASK 0x1f 25 #define VPE_PID_FUNC_MASK 0xfff 27 #define VPE_PID_SCHEME_MASK 0x03 30 #define VPE_SYSCONFIG 0x0010 31 #define VPE_SYSCONFIG_IDLE_MASK 0x03 [all …]
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/openbmc/linux/drivers/hwtracing/coresight/ |
H A D | coresight-priv.h | 16 * Coresight management registers (0xf00-0xfcc) 17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0 20 #define CORESIGHT_ITCTRL 0xf00 21 #define CORESIGHT_CLAIMSET 0xfa0 22 #define CORESIGHT_CLAIMCLR 0xfa4 23 #define CORESIGHT_LAR 0xfb0 24 #define CORESIGHT_LSR 0xfb4 25 #define CORESIGHT_DEVARCH 0xfbc 26 #define CORESIGHT_AUTHSTATUS 0xfb8 27 #define CORESIGHT_DEVID 0xfc8 [all …]
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H A D | coresight-tpiu.c | 22 #define TPIU_SUPP_PORTSZ 0x000 23 #define TPIU_CURR_PORTSZ 0x004 24 #define TPIU_SUPP_TRIGMODES 0x100 25 #define TPIU_TRIG_CNTRVAL 0x104 26 #define TPIU_TRIG_MULT 0x108 27 #define TPIU_SUPP_TESTPATM 0x200 28 #define TPIU_CURR_TESTPATM 0x204 29 #define TPIU_TEST_PATREPCNTR 0x208 30 #define TPIU_FFSR 0x300 31 #define TPIU_FFCR 0x304 [all …]
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/openbmc/linux/drivers/net/wireless/ath/ath12k/ |
H A D | hal.h | 36 #define HAL_SHADOW_BASE_ADDR 0x000008fc 44 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 45 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 46 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 47 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000 48 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x01b81000 49 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x01b82000 50 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x01b83000 51 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 53 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 [all …]
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/openbmc/u-boot/arch/powerpc/include/asm/ |
H A D | mpc8349_pci.h | 5 #define M8265_PCIBR0 0x101ac 6 #define M8265_PCIBR1 0x101b0 7 #define M8265_PCIMSK0 0x101c4 8 #define M8265_PCIMSK1 0x101c8 12 #define PCIBR_ENABLE 0x00000001 16 #define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ 17 #define PCIMSK_64KB 0xFFFF0000 18 #define PCIMSK_128KB 0xFFFE0000 19 #define PCIMSK_256KB 0xFFFC0000 20 #define PCIMSK_512KB 0xFFF80000 [all …]
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/openbmc/linux/drivers/net/ethernet/intel/igc/ |
H A D | igc_diag.c | 8 { IGC_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 9 { IGC_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 10 { IGC_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 11 { IGC_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 12 { IGC_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, 13 { IGC_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 14 { IGC_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 15 { IGC_FCRTH, 1, PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 }, 16 { IGC_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 17 { IGC_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, [all …]
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
H A D | at91_pit.h | 16 u32 mr; /* 0x00 Mode Register */ 17 u32 sr; /* 0x04 Status Register */ 18 u32 pivr; /* 0x08 Periodic Interval Value Register */ 19 u32 piir; /* 0x0C Periodic Interval Image Register */ 22 #define AT91_PIT_MR_IEN 0x02000000 23 #define AT91_PIT_MR_EN 0x01000000 24 #define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
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/openbmc/qemu/tests/tcg/xtensa/ |
H A D | test_mmu.S | 6 #define BASE 0x20000000 7 #define TLB_BASE 0x80000000 23 clean_tlb_way 0, 0x00001000, 4 24 clean_tlb_way 1, 0x00001000, 4 25 clean_tlb_way 2, 0x00001000, 4 26 clean_tlb_way 3, 0x00001000, 4 27 clean_tlb_way 4, 0x00100000, 4 28 movi a2, 0x00000007 30 movi a2, 0x00000008 32 movi a2, 0x00000009 [all …]
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-test/fwts/fwts/ |
H A D | 0005-Undefine-PAGE_SIZE.patch | 19 #define BIOS_START (0x000e0000) /* Start of BIOS memory */ 20 #define BIOS_END (0x000fffff) /* End of BIOS memory */
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/openbmc/linux/drivers/net/wireless/ath/ath11k/ |
H A D | hal.h | 43 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 44 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 54 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 56 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 57 #define HAL_WLAON_REG_BASE 0x01f80000 60 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 61 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 105 #define HAL_TCL1_RING_HP 0x00002000 106 #define HAL_TCL1_RING_TP 0x00002004 [all …]
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/openbmc/linux/drivers/net/wireless/ath/ath9k/ |
H A D | ar9002_phy.h | 19 #define AR_PHY_TEST 0x9800 20 #define PHY_AGC_CLR 0x10000000 21 #define RFSILENT_BB 0x00002000 23 #define AR_PHY_TURBO 0x9804 24 #define AR_PHY_FC_TURBO_MODE 0x00000001 25 #define AR_PHY_FC_TURBO_SHORT 0x00000002 26 #define AR_PHY_FC_DYN2040_EN 0x00000004 27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 [all …]
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/openbmc/linux/arch/parisc/mm/ |
H A D | ioremap.c | 22 if ((phys_addr >= 0x00080000 && end < 0x000fffff) || in ioremap_prot() 23 (phys_addr >= 0x00500000 && end < 0x03bfffff)) in ioremap_prot() 24 phys_addr |= F_EXTEND(0xfc000000); in ioremap_prot()
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/openbmc/linux/arch/arm/include/debug/ |
H A D | imx.S | 20 (((x) & 0x80000000) >> 7) | \ 21 (0xf4000000 + \ 22 (((x) & 0x50000000) >> 6) + \ 23 (((x) & 0x0b000000) >> 4) + \ 24 (((x) & 0x000fffff)))) 35 str \rd, [\rx, #0x40] @ TXDATA 45 1002: ldr \rd, [\rx, #0x98] @ SR2
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