xref: /openbmc/linux/drivers/gpu/drm/radeon/r600_reg.h (revision a69e40fd)
1771fe6b9SJerome Glisse /*
2771fe6b9SJerome Glisse  * Copyright 2008 Advanced Micro Devices, Inc.
3771fe6b9SJerome Glisse  * Copyright 2008 Red Hat Inc.
4771fe6b9SJerome Glisse  * Copyright 2009 Jerome Glisse.
5771fe6b9SJerome Glisse  *
6771fe6b9SJerome Glisse  * Permission is hereby granted, free of charge, to any person obtaining a
7771fe6b9SJerome Glisse  * copy of this software and associated documentation files (the "Software"),
8771fe6b9SJerome Glisse  * to deal in the Software without restriction, including without limitation
9771fe6b9SJerome Glisse  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10771fe6b9SJerome Glisse  * and/or sell copies of the Software, and to permit persons to whom the
11771fe6b9SJerome Glisse  * Software is furnished to do so, subject to the following conditions:
12771fe6b9SJerome Glisse  *
13771fe6b9SJerome Glisse  * The above copyright notice and this permission notice shall be included in
14771fe6b9SJerome Glisse  * all copies or substantial portions of the Software.
15771fe6b9SJerome Glisse  *
16771fe6b9SJerome Glisse  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17771fe6b9SJerome Glisse  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18771fe6b9SJerome Glisse  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19771fe6b9SJerome Glisse  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20771fe6b9SJerome Glisse  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21771fe6b9SJerome Glisse  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22771fe6b9SJerome Glisse  * OTHER DEALINGS IN THE SOFTWARE.
23771fe6b9SJerome Glisse  *
24771fe6b9SJerome Glisse  * Authors: Dave Airlie
25771fe6b9SJerome Glisse  *          Alex Deucher
26771fe6b9SJerome Glisse  *          Jerome Glisse
27771fe6b9SJerome Glisse  */
28771fe6b9SJerome Glisse #ifndef __R600_REG_H__
29771fe6b9SJerome Glisse #define __R600_REG_H__
30771fe6b9SJerome Glisse 
31771fe6b9SJerome Glisse #define R600_PCIE_PORT_INDEX                0x0038
32771fe6b9SJerome Glisse #define R600_PCIE_PORT_DATA                 0x003c
33771fe6b9SJerome Glisse 
34ff82bbc4SAlex Deucher #define R600_RCU_INDEX                      0x0100
35ff82bbc4SAlex Deucher #define R600_RCU_DATA                       0x0104
36ff82bbc4SAlex Deucher 
3793656cddSAlex Deucher #define R600_UVD_CTX_INDEX                  0xf4a0
3893656cddSAlex Deucher #define R600_UVD_CTX_DATA                   0xf4a4
3993656cddSAlex Deucher 
40771fe6b9SJerome Glisse #define R600_MC_VM_FB_LOCATION			0x2180
41771fe6b9SJerome Glisse #define		R600_MC_FB_BASE_MASK			0x0000FFFF
42771fe6b9SJerome Glisse #define		R600_MC_FB_BASE_SHIFT			0
43771fe6b9SJerome Glisse #define		R600_MC_FB_TOP_MASK			0xFFFF0000
44771fe6b9SJerome Glisse #define		R600_MC_FB_TOP_SHIFT			16
45771fe6b9SJerome Glisse #define R600_MC_VM_AGP_TOP			0x2184
46771fe6b9SJerome Glisse #define		R600_MC_AGP_TOP_MASK			0x0003FFFF
47771fe6b9SJerome Glisse #define		R600_MC_AGP_TOP_SHIFT			0
48771fe6b9SJerome Glisse #define R600_MC_VM_AGP_BOT			0x2188
49771fe6b9SJerome Glisse #define		R600_MC_AGP_BOT_MASK			0x0003FFFF
50771fe6b9SJerome Glisse #define		R600_MC_AGP_BOT_SHIFT			0
51771fe6b9SJerome Glisse #define R600_MC_VM_AGP_BASE			0x218c
52771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2190
53771fe6b9SJerome Glisse #define		R600_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
54771fe6b9SJerome Glisse #define		R600_LOGICAL_PAGE_NUMBER_SHIFT		0
55771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2194
56771fe6b9SJerome Glisse #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x2198
57771fe6b9SJerome Glisse 
58771fe6b9SJerome Glisse #define R700_MC_VM_FB_LOCATION			0x2024
59771fe6b9SJerome Glisse #define		R700_MC_FB_BASE_MASK			0x0000FFFF
60771fe6b9SJerome Glisse #define		R700_MC_FB_BASE_SHIFT			0
61771fe6b9SJerome Glisse #define		R700_MC_FB_TOP_MASK			0xFFFF0000
62771fe6b9SJerome Glisse #define		R700_MC_FB_TOP_SHIFT			16
63771fe6b9SJerome Glisse #define R700_MC_VM_AGP_TOP			0x2028
64771fe6b9SJerome Glisse #define		R700_MC_AGP_TOP_MASK			0x0003FFFF
65771fe6b9SJerome Glisse #define		R700_MC_AGP_TOP_SHIFT			0
66771fe6b9SJerome Glisse #define R700_MC_VM_AGP_BOT			0x202c
67771fe6b9SJerome Glisse #define		R700_MC_AGP_BOT_MASK			0x0003FFFF
68771fe6b9SJerome Glisse #define		R700_MC_AGP_BOT_SHIFT			0
69771fe6b9SJerome Glisse #define R700_MC_VM_AGP_BASE			0x2030
70771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR	0x2034
71771fe6b9SJerome Glisse #define		R700_LOGICAL_PAGE_NUMBER_MASK		0x000FFFFF
72771fe6b9SJerome Glisse #define		R700_LOGICAL_PAGE_NUMBER_SHIFT		0
73771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR	0x2038
74771fe6b9SJerome Glisse #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR	0x203c
75771fe6b9SJerome Glisse 
76771fe6b9SJerome Glisse #define R600_RAMCFG				       0x2408
77771fe6b9SJerome Glisse #       define R600_CHANSIZE                           (1 << 7)
78771fe6b9SJerome Glisse #       define R600_CHANSIZE_OVERRIDE                  (1 << 10)
79771fe6b9SJerome Glisse 
80771fe6b9SJerome Glisse 
81771fe6b9SJerome Glisse #define R600_GENERAL_PWRMGT                                        0x618
82771fe6b9SJerome Glisse #	define R600_OPEN_DRAIN_PADS				   (1 << 11)
83771fe6b9SJerome Glisse 
84771fe6b9SJerome Glisse #define R600_LOWER_GPIO_ENABLE                                     0x710
85771fe6b9SJerome Glisse #define R600_CTXSW_VID_LOWER_GPIO_CNTL                             0x718
86771fe6b9SJerome Glisse #define R600_HIGH_VID_LOWER_GPIO_CNTL                              0x71c
87771fe6b9SJerome Glisse #define R600_MEDIUM_VID_LOWER_GPIO_CNTL                            0x720
88771fe6b9SJerome Glisse #define R600_LOW_VID_LOWER_GPIO_CNTL                               0x724
89771fe6b9SJerome Glisse 
90fa6bee46SAlex Deucher #define R600_D1GRPH_SWAP_CONTROL                     0x610C
91a69e40fdSMauro Rossi #       define R600_D1GRPH_ENDIAN_SWAP(x)            (((x) & 0x3) << 0)
92a69e40fdSMauro Rossi #       define R600_D1GRPH_SWAP_ENDIAN_NONE          0
93a69e40fdSMauro Rossi #       define R600_D1GRPH_SWAP_ENDIAN_16BIT         1
94a69e40fdSMauro Rossi #       define R600_D1GRPH_SWAP_ENDIAN_32BIT         2
95a69e40fdSMauro Rossi #       define R600_D1GRPH_SWAP_ENDIAN_64BIT         3
96a69e40fdSMauro Rossi #       define R600_D1GRPH_RED_CROSSBAR(x)           (((x) & 0x3) << 4)
97a69e40fdSMauro Rossi #       define R600_D1GRPH_RED_SEL_R                 0
98a69e40fdSMauro Rossi #       define R600_D1GRPH_RED_SEL_G                 1
99a69e40fdSMauro Rossi #       define R600_D1GRPH_RED_SEL_B                 2
100a69e40fdSMauro Rossi #       define R600_D1GRPH_RED_SEL_A                 3
101a69e40fdSMauro Rossi #       define R600_D1GRPH_GREEN_CROSSBAR(x)         (((x) & 0x3) << 6)
102a69e40fdSMauro Rossi #       define R600_D1GRPH_GREEN_SEL_G               0
103a69e40fdSMauro Rossi #       define R600_D1GRPH_GREEN_SEL_B               1
104a69e40fdSMauro Rossi #       define R600_D1GRPH_GREEN_SEL_A               2
105a69e40fdSMauro Rossi #       define R600_D1GRPH_GREEN_SEL_R               3
106a69e40fdSMauro Rossi #       define R600_D1GRPH_BLUE_CROSSBAR(x)          (((x) & 0x3) << 8)
107a69e40fdSMauro Rossi #       define R600_D1GRPH_BLUE_SEL_B                0
108a69e40fdSMauro Rossi #       define R600_D1GRPH_BLUE_SEL_A                1
109a69e40fdSMauro Rossi #       define R600_D1GRPH_BLUE_SEL_R                2
110a69e40fdSMauro Rossi #       define R600_D1GRPH_BLUE_SEL_G                3
111a69e40fdSMauro Rossi #       define R600_D1GRPH_ALPHA_CROSSBAR(x)         (((x) & 0x3) << 10)
112a69e40fdSMauro Rossi #       define R600_D1GRPH_ALPHA_SEL_A               0
113a69e40fdSMauro Rossi #       define R600_D1GRPH_ALPHA_SEL_R               1
114a69e40fdSMauro Rossi #       define R600_D1GRPH_ALPHA_SEL_G               2
115a69e40fdSMauro Rossi #       define R600_D1GRPH_ALPHA_SEL_B               3
116771fe6b9SJerome Glisse 
117771fe6b9SJerome Glisse #define R600_HDP_NONSURFACE_BASE                                0x2c04
118771fe6b9SJerome Glisse 
119771fe6b9SJerome Glisse #define R600_BUS_CNTL                                           0x5420
1200ec80d64SAlex Deucher #       define R600_BIOS_ROM_DIS                                (1 << 1)
121771fe6b9SJerome Glisse #define R600_CONFIG_CNTL                                        0x5424
122771fe6b9SJerome Glisse #define R600_CONFIG_MEMSIZE                                     0x5428
123771fe6b9SJerome Glisse #define R600_CONFIG_F0_BASE                                     0x542C
124771fe6b9SJerome Glisse #define R600_CONFIG_APER_SIZE                                   0x5430
125771fe6b9SJerome Glisse 
1266253e4c7SAlex Deucher #define	R600_BIF_FB_EN						0x5490
1276253e4c7SAlex Deucher #define		R600_FB_READ_EN					(1 << 0)
1286253e4c7SAlex Deucher #define		R600_FB_WRITE_EN				(1 << 1)
1296253e4c7SAlex Deucher 
1306253e4c7SAlex Deucher #define R600_CITF_CNTL           				0x200c
1316253e4c7SAlex Deucher #define		R600_BLACKOUT_MASK				0x00000003
1326253e4c7SAlex Deucher 
1336253e4c7SAlex Deucher #define R700_MC_CITF_CNTL           				0x25c0
1346253e4c7SAlex Deucher 
135771fe6b9SJerome Glisse #define R600_ROM_CNTL                              0x1600
136771fe6b9SJerome Glisse #       define R600_SCK_OVERWRITE                  (1 << 1)
137771fe6b9SJerome Glisse #       define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
138771fe6b9SJerome Glisse #       define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK  (0xf << 28)
139771fe6b9SJerome Glisse 
140771fe6b9SJerome Glisse #define R600_CG_SPLL_FUNC_CNTL                     0x600
141771fe6b9SJerome Glisse #       define R600_SPLL_BYPASS_EN                 (1 << 3)
142771fe6b9SJerome Glisse #define R600_CG_SPLL_STATUS                        0x60c
143771fe6b9SJerome Glisse #       define R600_SPLL_CHG_STATUS                (1 << 1)
144771fe6b9SJerome Glisse 
145771fe6b9SJerome Glisse #define R600_BIOS_0_SCRATCH               0x1724
146771fe6b9SJerome Glisse #define R600_BIOS_1_SCRATCH               0x1728
147771fe6b9SJerome Glisse #define R600_BIOS_2_SCRATCH               0x172c
148771fe6b9SJerome Glisse #define R600_BIOS_3_SCRATCH               0x1730
149771fe6b9SJerome Glisse #define R600_BIOS_4_SCRATCH               0x1734
150771fe6b9SJerome Glisse #define R600_BIOS_5_SCRATCH               0x1738
151771fe6b9SJerome Glisse #define R600_BIOS_6_SCRATCH               0x173c
152771fe6b9SJerome Glisse #define R600_BIOS_7_SCRATCH               0x1740
153771fe6b9SJerome Glisse 
154dafc3bd5SChristian Koenig /* Audio, these regs were reverse enginered,
155dafc3bd5SChristian Koenig  * so the chance is high that the naming is wrong
156dafc3bd5SChristian Koenig  * R6xx+ ??? */
157dafc3bd5SChristian Koenig 
158dafc3bd5SChristian Koenig /* Audio clocks */
159dafc3bd5SChristian Koenig #define R600_AUDIO_PLL1_MUL               0x0514
160dafc3bd5SChristian Koenig #define R600_AUDIO_PLL1_DIV               0x0518
161dafc3bd5SChristian Koenig #define R600_AUDIO_PLL2_MUL               0x0524
162dafc3bd5SChristian Koenig #define R600_AUDIO_PLL2_DIV               0x0528
163dafc3bd5SChristian Koenig #define R600_AUDIO_CLK_SRCSEL             0x0534
164dafc3bd5SChristian Koenig 
165dafc3bd5SChristian Koenig /* Audio general */
166dafc3bd5SChristian Koenig #define R600_AUDIO_ENABLE                 0x7300
167dafc3bd5SChristian Koenig #define R600_AUDIO_TIMING                 0x7344
168dafc3bd5SChristian Koenig 
169dafc3bd5SChristian Koenig /* Audio params */
170dafc3bd5SChristian Koenig #define R600_AUDIO_VENDOR_ID              0x7380
171dafc3bd5SChristian Koenig #define R600_AUDIO_REVISION_ID            0x7384
172dafc3bd5SChristian Koenig #define R600_AUDIO_ROOT_NODE_COUNT        0x7388
173dafc3bd5SChristian Koenig #define R600_AUDIO_NID1_NODE_COUNT        0x738c
174dafc3bd5SChristian Koenig #define R600_AUDIO_NID1_TYPE              0x7390
175dafc3bd5SChristian Koenig #define R600_AUDIO_SUPPORTED_SIZE_RATE    0x7394
176dafc3bd5SChristian Koenig #define R600_AUDIO_SUPPORTED_CODEC        0x7398
177dafc3bd5SChristian Koenig #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
178dafc3bd5SChristian Koenig #define R600_AUDIO_NID2_CAPS              0x73a0
179dafc3bd5SChristian Koenig #define R600_AUDIO_NID3_CAPS              0x73a4
180dafc3bd5SChristian Koenig #define R600_AUDIO_NID3_PIN_CAPS          0x73a8
181dafc3bd5SChristian Koenig 
182dafc3bd5SChristian Koenig /* Audio conn list */
183dafc3bd5SChristian Koenig #define R600_AUDIO_CONN_LIST_LEN          0x73ac
184dafc3bd5SChristian Koenig #define R600_AUDIO_CONN_LIST              0x73b0
185dafc3bd5SChristian Koenig 
186dafc3bd5SChristian Koenig /* Audio verbs */
187dafc3bd5SChristian Koenig #define R600_AUDIO_RATE_BPS_CHANNEL       0x73c0
188dafc3bd5SChristian Koenig #define R600_AUDIO_PLAYING                0x73c4
189dafc3bd5SChristian Koenig #define R600_AUDIO_IMPLEMENTATION_ID      0x73c8
190dafc3bd5SChristian Koenig #define R600_AUDIO_CONFIG_DEFAULT         0x73cc
191dafc3bd5SChristian Koenig #define R600_AUDIO_PIN_SENSE              0x73d0
192dafc3bd5SChristian Koenig #define R600_AUDIO_PIN_WIDGET_CNTL        0x73d4
193dafc3bd5SChristian Koenig #define R600_AUDIO_STATUS_BITS            0x73d8
194dafc3bd5SChristian Koenig 
1950783986aSAlex Deucher #define DCE2_HDMI_OFFSET0		(0x7400 - 0x7400)
1960783986aSAlex Deucher #define DCE2_HDMI_OFFSET1		(0x7700 - 0x7400)
1970783986aSAlex Deucher /* DCE3.2 second instance starts at 0x7800 */
1980783986aSAlex Deucher #define DCE3_HDMI_OFFSET0		(0x7400 - 0x7400)
1990783986aSAlex Deucher #define DCE3_HDMI_OFFSET1		(0x7800 - 0x7400)
2000783986aSAlex Deucher 
201771fe6b9SJerome Glisse #endif
202