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/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h21 * configured, and a value of 0 otherwise. These macros are always defined.
38 #define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */
39 #define XCHAL_HAVE_SEXT 0 /* SEXT instruction */
40 #define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
41 #define XCHAL_HAVE_MUL16 0 /* MUL16S/MUL16U instructions */
42 #define XCHAL_HAVE_MUL32 0 /* MULL instruction */
43 #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
46 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
48 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
49 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
[all …]
/openbmc/u-boot/include/configs/
H A Dedminiv2.h18 #define CONFIG_SPL_TEXT_BASE 0xffff0000
19 #define CONFIG_SPL_MAX_SIZE 0x0000fff0
20 #define CONFIG_SPL_STACK 0x00020000
21 #define CONFIG_SPL_BSS_START_ADDR 0x00020000
22 #define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
23 #define CONFIG_SYS_SPL_MALLOC_START 0x00040000
24 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
25 #define CONFIG_SYS_UBOOT_BASE 0xfff90000
26 #define CONFIG_SYS_UBOOT_START 0x00800000
44 * MPP16 to MPP19, mode 0 for others
[all …]
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h20 * configured, and a value of 0 otherwise. These macros are always defined.
37 #define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */
38 #define XCHAL_HAVE_SEXT 0 /* SEXT instruction */
39 #define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
40 #define XCHAL_HAVE_MUL16 0 /* MUL16S/MUL16U instructions */
41 #define XCHAL_HAVE_MUL32 0 /* MULL instruction */
42 #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
45 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
47 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
48 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
[all …]
/openbmc/linux/drivers/net/wireless/ti/wl1251/
H A Dspi.h16 #define WSPI_CMD_READ 0x40000000
17 #define WSPI_CMD_WRITE 0x00000000
18 #define WSPI_CMD_FIXED 0x20000000
19 #define WSPI_CMD_BYTE_LENGTH 0x1FFE0000
21 #define WSPI_CMD_BYTE_ADDR 0x0001FFFF
25 #define WSPI_INIT_CMD_START 0x00
26 #define WSPI_INIT_CMD_TX 0x40
28 #define WSPI_INIT_CMD_BYPASS_BIT 0x80
29 #define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
30 #define WSPI_INIT_CMD_EN_FIXEDBUSY 0x80
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-arm7tdmi.S78 extra_hwcaps=0
83 .long 0
84 .long 0
91 .long 0
92 .long 0
97 arm7tdmi_proc_info arm7tdmi, 0x41007700, 0xfff8ff00, \
99 arm7tdmi_proc_info triscenda7, 0x0001d2ff, 0x0001ffff, \
101 arm7tdmi_proc_info at91, 0x14000040, 0xfff000e0, \
103 arm7tdmi_proc_info s3c4510b, 0x36365000, 0xfffff000, \
105 arm7tdmi_proc_info s3c4530, 0x4c000000, 0xfff000e0, \
[all …]
/openbmc/linux/drivers/mtd/maps/
H A Dcfi_flagadm.c36 * 1: bootloader first 128k (0x00000000 - 0x0001FFFF) size 0x020000
37 * 2: kernel 640k (0x00020000 - 0x000BFFFF) size 0x0A0000
38 * 3: compressed 1536k root ramdisk (0x000C0000 - 0x0023FFFF) size 0x180000
39 * 4: writeable diskpartition (jffs)(0x00240000 - 0x003FFFFF) size 0x1C0000
42 #define FLASH_PHYS_ADDR 0x40000000
43 #define FLASH_SIZE 0x400000
45 #define FLASH_PARTITION0_ADDR 0x00000000
46 #define FLASH_PARTITION0_SIZE 0x00020000
48 #define FLASH_PARTITION1_ADDR 0x00020000
49 #define FLASH_PARTITION1_SIZE 0x000A0000
[all …]
/openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
15 EMIT_MASKPOLL(0xf800010c, 0x00000001),
16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
18 EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220),
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_default.h28 #define regSDMA0_DEC_START_DEFAULT 0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
33 #define regSDMA0_CNTL_DEFAULT 0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbgmac.h9 #define BGMAC_DEV_CTL 0x000
10 #define BGMAC_DC_TSM 0x00000002
11 #define BGMAC_DC_CFCO 0x00000004
12 #define BGMAC_DC_RLSS 0x00000008
13 #define BGMAC_DC_MROR 0x00000010
14 #define BGMAC_DC_FCM_MASK 0x00000060
16 #define BGMAC_DC_NAE 0x00000080
17 #define BGMAC_DC_TF 0x00000100
18 #define BGMAC_DC_RDS_MASK 0x00030000
20 #define BGMAC_DC_TDS_MASK 0x000c0000
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/cbus/
H A Dclass_csr.h15 #define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
16 #define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
17 #define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
18 /* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
19 #define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
23 #define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
27 #define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
29 /* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
30 #define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
31 /* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv40.c47 nvkm_wo32(ramfc, base + 0x00, offset); in nv40_chan_ramfc_write()
48 nvkm_wo32(ramfc, base + 0x04, offset); in nv40_chan_ramfc_write()
49 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); in nv40_chan_ramfc_write()
50 nvkm_wo32(ramfc, base + 0x18, 0x30000000 | in nv40_chan_ramfc_write()
57 nvkm_wo32(ramfc, base + 0x3c, 0x0001ffff); in nv40_chan_ramfc_write()
59 return 0; in nv40_chan_ramfc_write()
65 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
66 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
67 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
68 { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmnv44.c30 u32 pteo = (ptei << 2) & ~0x0000000f; in nv44_vmm_pgt_fill()
33 tmp[0] = nvkm_ro32(pt->memory, pteo + 0x0); in nv44_vmm_pgt_fill()
34 tmp[1] = nvkm_ro32(pt->memory, pteo + 0x4); in nv44_vmm_pgt_fill()
35 tmp[2] = nvkm_ro32(pt->memory, pteo + 0x8); in nv44_vmm_pgt_fill()
36 tmp[3] = nvkm_ro32(pt->memory, pteo + 0xc); in nv44_vmm_pgt_fill()
40 switch (ptei++ & 0x3) { in nv44_vmm_pgt_fill()
41 case 0: in nv44_vmm_pgt_fill()
42 tmp[0] &= ~0x07ffffff; in nv44_vmm_pgt_fill()
43 tmp[0] |= addr; in nv44_vmm_pgt_fill()
46 tmp[0] &= ~0xf8000000; in nv44_vmm_pgt_fill()
[all …]
/openbmc/qemu/target/ppc/
H A Dmmu_helper.c51 for (nr = 0; nr < max; nr++) { in ppc6xx_tlb_invalidate_all()
68 for (way = 0; way < env->nb_ways; way++) { in ppc6xx_tlb_invalidate_virt2()
71 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { in ppc6xx_tlb_invalidate_virt2()
87 ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0); in ppc6xx_tlb_invalidate_virt()
116 for (i = 0; i < env->nb_tlb; i++) { in ppc4xx_tlb_invalidate_all()
130 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { in booke206_flush_tlb()
133 for (j = 0; j < tlb_size; j++) { in booke206_flush_tlb()
154 base = BATu & ~0x0001FFFF; in do_invalidate_BAT()
155 end = base + mask + 0x00020000; in do_invalidate_BAT()
177 TARGET_FMT_lx ")\n", ID, nr, ul == 0 ? 'u' : 'l', in dump_store_bat()
[all …]
/openbmc/linux/include/acpi/
H A Dacoutput.h21 #define ACPI_UTILITIES 0x00000001
22 #define ACPI_HARDWARE 0x00000002
23 #define ACPI_EVENTS 0x00000004
24 #define ACPI_TABLES 0x00000008
25 #define ACPI_NAMESPACE 0x00000010
26 #define ACPI_PARSER 0x00000020
27 #define ACPI_DISPATCHER 0x00000040
28 #define ACPI_EXECUTER 0x00000080
29 #define ACPI_RESOURCES 0x00000100
30 #define ACPI_CA_DEBUGGER 0x00000200
[all …]
/openbmc/linux/drivers/net/wireless/ti/wlcore/
H A Dspi.c25 #define WSPI_CMD_READ 0x40000000
26 #define WSPI_CMD_WRITE 0x00000000
27 #define WSPI_CMD_FIXED 0x20000000
28 #define WSPI_CMD_BYTE_LENGTH 0x1FFE0000
30 #define WSPI_CMD_BYTE_ADDR 0x0001FFFF
34 #define WSPI_INIT_CMD_START 0x00
35 #define WSPI_INIT_CMD_TX 0x40
37 #define WSPI_INIT_CMD_BYPASS_BIT 0x80
38 #define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
39 #define WSPI_INIT_CMD_EN_FIXEDBUSY 0x80
[all …]
/openbmc/qemu/docs/specs/
H A Drocker.rst34 * Use of leading 0x indicates a hexadecimal number.
35 * Use of leading 0b indicates a binary number.
54 0x0 2 Vendor ID 0x1b36
55 0x2 2 Device ID 0x0006
56 0x4 4 Command/Status
57 0x8 1 Revision ID 0x01
58 0x9 3 Class code 0x2800
59 0xC 1 Cache line size
60 0xD 1 Latency timer
61 0xE 1 Header type
[all …]
/openbmc/linux/include/linux/
H A Drio.h25 #define RIO_INVALID_DESTID 0xffff
32 #define RIO_GLOBAL_TABLE 0xff /* Indicates access of a switch's
37 #define RIO_INVALID_ROUTE 0xff /* Indicates that a route table
42 #define RIO_ANY_DESTID(size) (size ? 0xffff : 0xff)
45 #define RIO_MAX_MSG_SIZE 0x1000
50 #define RIO_SUCCESSFUL 0x00
51 #define RIO_BAD_SIZE 0x81
56 * 0 RapidIO outbound doorbells
61 * 0 RapidIO inbound doorbells
65 #define RIO_DOORBELL_RESOURCE 0
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/openbmc/linux/drivers/net/ethernet/dec/tulip/
H A Dinterrupt.c22 #define MIT_TABLE 15 /* We use 0 or max */
38 0x0, /* IM disabled */
39 0x80150000, /* RX time = 1, RX pkts = 2, CM = 1 */
40 0x80150000,
41 0x80270000,
42 0x80370000,
43 0x80490000,
44 0x80590000,
45 0x80690000,
46 0x807B0000,
[all …]

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