Lines Matching +full:0 +full:x0001ffff
34 * Use of leading 0x indicates a hexadecimal number.
35 * Use of leading 0b indicates a binary number.
54 0x0 2 Vendor ID 0x1b36
55 0x2 2 Device ID 0x0006
56 0x4 4 Command/Status
57 0x8 1 Revision ID 0x01
58 0x9 3 Class code 0x2800
59 0xC 1 Cache line size
60 0xD 1 Latency timer
61 0xE 1 Header type
62 0xF 1 Built-in self test
63 0x10 4 Base address low
64 0x14 4 Base address high
65 0x18-28 Reserved
66 0x2C 2 Subsystem vendor ID *
67 0x2E 2 Subsystem ID *
68 0x30-38 Reserved
69 0x3C 1 Interrupt line
70 0x3D 1 Interrupt pin 0x00
71 0x3E 1 Min grant 0x00
72 0x3D 1 Max latency 0x00
73 0x40 1 TRDY timeout
74 0x41 1 Retry count
75 0x42 2 Reserved
83 0x2000 in size. BAR1 maps MSI-X vector and PBA tables and is also 0x2000 in
95 0x0000-0x000f Bogus registers to catch misbehaving
97 back as 0xDEADBABE.
98 0x0010-0x00ff Test registers
99 0x0300-0x03ff General purpose registers
100 0x1000-0x1fff Descriptor control
103 Reads to reserved registers read back as 0.
111 0x0000-0x0fff MSI-X vector table (256 vectors total)
112 0x1000-0x1fff MSI-X PBA table
128 0 Command descriptor ring completion
140 lower_addr 0x0 4 [31:2] message address[31:2]
141 [1:0] Rsvd (4 byte alignment
143 upper_addr 0x4 4 [31:19] Rsvd
144 [14:0] message address[46:32]
145 data 0x8 4 message data[31:0]
146 control 0xc 4 [31:1] Rsvd
147 [0] mask (0 = enable,
174 DMA_DESC_xxx_BASE_ADDR, offset 0x1000 + (x * 32), 64-bit, (R/W)
175 DMA_DESC_xxx_SIZE, offset 0x1008 + (x * 32), 32-bit, (R/W)
176 DMA_DESC_xxx_HEAD, offset 0x100c + (x * 32), 32-bit, (R/W)
177 DMA_DESC_xxx_TAIL, offset 0x1010 + (x * 32), 32-bit, (R)
178 DMA_DESC_xxx_CTRL, offset 0x1014 + (x * 32), 32-bit, (W)
179 DMA_DESC_xxx_CREDITS, offset 0x1018 + (x * 32), 32-bit, (R/W)
180 DMA_DESC_xxx_RSVD1, offset 0x101c + (x * 32), 32-bit, (R/W)
186 0 CMD
188 2 TX (port 0)
189 3 RX (port 0)
209 [0] CTRL_RESET Reset the descriptor ring
324 TEST_REG, offset 0x0010, 32-bit (R/W)
325 TEST_REG64, offset 0x0018, 64-bit (R/W)
326 TEST_IRQ, offset 0x0020, 32-bit (R/W)
327 TEST_DMA_ADDR, offset 0x0028, 64-bit (R/W)
328 TEST_DMA_SIZE, offset 0x0030, 32-bit (R/W)
329 TEST_DMA_CTRL, offset 0x0034, 32-bit (R/W)
345 TEST_DMA_CTRL_FILL 2 fill buffer bytes with 0x96
362 PORT_PHYS_COUNT, offset 0x0304, 32-bit, (R)
368 space. A special CPU port is assigned port 0. The front-panel ports are
370 tunnel ports are assigned ports 0x0001000-0x0001ffff.
375 0 CPU port (for packets to/from host CPU)
378 64-0x0000ffff RSVD
379 0x00010000-0x0001ffff logical tunnel ports
380 0x00020000-0xffffffff RSVD
395 PORT_PHYS_LINK_STATUS, offset 0x0310, 64-bit, (R)
397 Value is port bitmap. Bits 0 and 63 always read 0. Bits 1-62
398 read 1 for link UP and 0 for link DOWN for respective front-panel ports.
415 DUPLEX 1 1 = Full, 0 = Half
416 AUTONEG 1 1 = enabled, 0 = disabled
418 MODE 1 0 = OF-DPA
421 0 = disabled
431 DUPLEX 1 1 = Full, 0 = Half
432 AUTONEG 1 1 = enabled, 0 = disabled
434 MODE 1 0 = OF-DPA
442 PORT_PHYS_ENABLE: offset 0x0318, 64-bit, (R/W)
444 Value is bitmap of first 64 ports. Bits 0 and 63 are ignored
445 and always read as 0. Write 1 to enable port; write 0 to disable it.
446 Default is 0.
459 CONTROL: offset 0x0300, 32-bit, (W)
463 [0] CONTROL_RESET If set, device will perform reset
472 SWITCH_ID: offset 0x0320, 64-bit, (R)
500 0: down
554 | desc 0 | | +–––––+ +–––––––+ |
580 0: no offload
608 0 OK
633 (1 << 0): IPv4 packet
657 0 OK
713 0: ingress port
727 Table ID 0: ingress port::
750 OF_DPA_ETHERTYPE 2 (N) must be either 0x0800 or 0x86dd
765 OF_DPA_ETHERTYPE 2 (N) must be either 0x0800 or 0x86dd
780 OF_DPA_ETHERTYPE 2 (N) must be either 0x0800 or 0x86dd
820 set to 0 otherwise
856 == 0x0806.
885 logical port, set to 0
889 set to 0 otherwise
914 0 all OK
946 0: L2 interface
955 FLOW_VLAN_ID 2 Vlan ID (types 0, 3, 4, 6)
956 FLOW_L2_PORT 2 Port (types 0)
957 FLOW_INDEX 4 Index (all types but 0)
959 0: Flood unicast tunnel
965 types except 0)
966 FLOW_OUT_PORT 4 egress port (types 0, 8)
994 0 all OK