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/openbmc/linux/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c38 #define MC_CG_ARB_FREQ_F0 0x0a
39 #define MC_CG_ARB_FREQ_F1 0x0b
40 #define MC_CG_ARB_FREQ_F2 0x0c
41 #define MC_CG_ARB_FREQ_F3 0x0d
43 #define MC_CG_SEQ_DRAMCONF_S0 0x05
44 #define MC_CG_SEQ_DRAMCONF_S1 0x06
45 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
46 #define MC_CG_SEQ_YCLK_RESUME 0x0a
48 #define SMC_RAM_END 0x8000
59 0x000008f8, 0x00000010, 0xffffffff,
[all …]
H A Devergreen.c49 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
50 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
51 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
62 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
73 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
84 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
95 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
106 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
117 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
136 0x98fc,
[all …]
H A Dni_dpm.c37 #define MC_CG_ARB_FREQ_F0 0x0a
38 #define MC_CG_ARB_FREQ_F1 0x0b
39 #define MC_CG_ARB_FREQ_F2 0x0c
40 #define MC_CG_ARB_FREQ_F3 0x0d
42 #define SMC_RAM_END 0xC000
46 0x15,
47 0x2,
48 0x19,
49 0x2,
50 0x8,
[all …]
H A Dtrinity_dpm.c45 0x0000802c, 0xc0000000, 0xffffffff,
46 0x00003fc4, 0xc0000000, 0xffffffff,
47 0x00005448, 0x00000100, 0xffffffff,
48 0x000055e4, 0x00000100, 0xffffffff,
49 0x0000160c, 0x00000100, 0xffffffff,
50 0x00008984, 0x06000100, 0xffffffff,
51 0x0000c164, 0x00000100, 0xffffffff,
52 0x00008a18, 0x00000100, 0xffffffff,
53 0x0000897c, 0x06000100, 0xffffffff,
54 0x00008b28, 0x00000100, 0xffffffff,
[all …]
H A Dni.c71 0x98fc,
72 0x98f0,
73 0x9834,
74 0x9838,
75 0x9870,
76 0x9874,
77 0x8a14,
78 0x8b24,
79 0x8bcc,
80 0x8b10,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspberrypi-fw-defs.h15 RPI_FWREQ_PROPERTY_END = 0,
16 RPI_FWREQ_GET_FIRMWARE_REVISION = 0x00000001,
17 RPI_FWREQ_GET_FIRMWARE_VARIANT = 0x00000002,
18 RPI_FWREQ_GET_FIRMWARE_HASH = 0x00000003,
20 RPI_FWREQ_SET_CURSOR_INFO = 0x00008010,
21 RPI_FWREQ_SET_CURSOR_STATE = 0x00008011,
23 RPI_FWREQ_GET_BOARD_MODEL = 0x00010001,
24 RPI_FWREQ_GET_BOARD_REVISION = 0x00010002,
25 RPI_FWREQ_GET_BOARD_MAC_ADDRESS = 0x00010003,
26 RPI_FWREQ_GET_BOARD_SERIAL = 0x00010004,
[all …]
/openbmc/linux/include/soc/bcm2835/
H A Draspberrypi-firmware.h15 RPI_FIRMWARE_STATUS_REQUEST = 0,
16 RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000,
17 RPI_FIRMWARE_STATUS_ERROR = 0x80000001,
37 RPI_FIRMWARE_PROPERTY_END = 0,
38 RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001,
40 RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010,
41 RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011,
43 RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001,
44 RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002,
45 RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003,
[all …]
/openbmc/qemu/hw/scsi/
H A Dsrp.h45 SRP_LOGIN_REQ = 0x00,
46 SRP_TSK_MGMT = 0x01,
47 SRP_CMD = 0x02,
48 SRP_I_LOGOUT = 0x03,
49 SRP_LOGIN_RSP = 0xc0,
50 SRP_RSP = 0xc1,
51 SRP_LOGIN_REJ = 0xc2,
52 SRP_T_LOGOUT = 0x80,
53 SRP_CRED_REQ = 0x81,
54 SRP_AER_REQ = 0x82,
[all …]
/openbmc/linux/include/scsi/
H A Dsrp.h48 SRP_LOGIN_REQ = 0x00,
49 SRP_TSK_MGMT = 0x01,
50 SRP_CMD = 0x02,
51 SRP_I_LOGOUT = 0x03,
52 SRP_LOGIN_RSP = 0xc0,
53 SRP_RSP = 0xc1,
54 SRP_LOGIN_REJ = 0xc2,
55 SRP_T_LOGOUT = 0x80,
56 SRP_CRED_REQ = 0x81,
57 SRP_AER_REQ = 0x82,
[all …]
/openbmc/u-boot/board/renesas/sh7785lcr/
H A Dlowlevel_init.S125 * 0 0xa0000000 0x00000000 1 64M 0 0
126 * 1 0xa4000000 0x04000000 1 16M 0 0
127 * 2 0xa6000000 0x08000000 1 16M 0 0
128 * 9 0x88000000 0x48000000 1 128M 1 1
129 * 10 0x90000000 0x50000000 1 128M 1 1
130 * 11 0x98000000 0x58000000 1 128M 1 1
131 * 13 0xa8000000 0x48000000 1 128M 0 0
132 * 14 0xb0000000 0x50000000 1 128M 0 0
133 * 15 0xb8000000 0x58000000 1 128M 0 0
168 PXCR_D: .word 0x0000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-imx8mq.dtsi47 reg = <0x00000000 0x40000000 0 0xc0000000>;
52 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
53 <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
82 reg = <0x0 0x30670000 0x0 0x10000>;
93 reg = <0x0 0x30200000 0x0 0x10000>;
104 reg = <0x0 0x30210000 0x0 0x10000>;
115 reg = <0x0 0x30220000 0x0 0x10000>;
126 reg = <0x0 0x30230000 0x0 0x10000>;
137 reg = <0x0 0x30240000 0x0 0x10000>;
148 reg = <0x0 0x30260000 0x0 0x10000>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1012a.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
85 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
[all …]
H A Dfsl-ls1046a.dtsi38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dfsl-ls1088a.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
/openbmc/linux/drivers/message/fusion/lsi/
H A Dmpi_log_sas.h16 #define SAS_LOGINFO_NEXUS_LOSS 0x31170000
17 #define SAS_LOGINFO_MASK 0xFFFF0000
20 /* IOC LOGINFO defines, 0x00000000 - 0x0FFFFFFF */
23 /* Bits 27-24: IOC_LOGINFO_ORIGINATOR: 0=IOP, 1=PL, 2=IR */
25 /* Bits 15-0: LOGINFO_CODE Specific */
31 #define IOC_LOGINFO_ORIGINATOR_IOP (0x00000000)
32 #define IOC_LOGINFO_ORIGINATOR_PL (0x01000000)
33 #define IOC_LOGINFO_ORIGINATOR_IR (0x02000000)
35 #define IOC_LOGINFO_ORIGINATOR_MASK (0x0F000000)
40 #define IOC_LOGINFO_CODE_MASK (0x00FF0000)
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
H A Dgf119.fuc4.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
H A Dgk208.fuc5.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
H A Dgt215.fuc3.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
H A Dgf100.fuc3.h3 /* 0x0000: proc_kern */
4 0x52544e49,
5 0x00000000,
6 0x00000000,
7 0x00000000,
8 0x00000000,
9 0x00000000,
10 0x00000000,
11 0x00000000,
12 0x00000000,
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a.dtsi31 #size-cells = <0>;
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
50 memory@0 {
52 reg = <0x0 0x0 0x0 0x0>;
57 #clock-cells = <0>;
80 offset = <0xb0>;
81 mask = <0x02>;
[all …]
/openbmc/qemu/hw/arm/
H A Dmusicpal.c43 #define MP_MISC_BASE 0x80002000
44 #define MP_MISC_SIZE 0x00001000
46 #define MP_ETH_BASE 0x80008000
48 #define MP_WLAN_BASE 0x8000C000
49 #define MP_WLAN_SIZE 0x00000800
51 #define MP_UART1_BASE 0x8000C840
52 #define MP_UART2_BASE 0x8000C940
54 #define MP_GPIO_BASE 0x8000D000
55 #define MP_GPIO_SIZE 0x00001000
57 #define MP_FLASHCFG_BASE 0x90006000
[all …]

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