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12

/openbmc/linux/tools/testing/selftests/powerpc/pmu/event_code_tests/
H A Devent_alternatives_tests_p10.c10 #define PM_RUN_CYC_ALT 0x200f4
11 #define PM_INST_DISP 0x200f2
12 #define PM_BR_2PATH 0x20036
13 #define PM_LD_MISS_L1 0x3e054
14 #define PM_RUN_INST_CMPL_ALT 0x400fa
16 #define EventCode_1 0x100fc
17 #define EventCode_2 0x200fa
18 #define EventCode_3 0x300fc
19 #define EventCode_4 0x400fc
44 * Test for event alternative for 0x0001e in event_alternatives_tests_p10()
[all …]
/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/include/uapi/asm-generic/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/openbmc/linux/arch/x86/events/
H A Dperf_event_flags.h5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
/openbmc/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_dpcd.h16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.h12 #define DPCD_RC00_DPCD_REV 0x00000
13 #define DPCD_RC01_MAX_LINK_RATE 0x00001
14 #define DPCD_RC02 0x00002
15 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80
16 #define DPCD_RC02_TPS3_SUPPORTED 0x40
17 #define DPCD_RC02_MAX_LANE_COUNT 0x1f
18 #define DPCD_RC03 0x00003
19 #define DPCD_RC03_TPS4_SUPPORTED 0x80
20 #define DPCD_RC03_MAX_DOWNSPREAD 0x01
21 #define DPCD_RC0E 0x0000e
[all …]
/openbmc/linux/arch/powerpc/perf/
H A Dpower10-events-list.h12 EVENT(PM_CYC, 0x600f4);
13 EVENT(PM_DISP_STALL_CYC, 0x100f8);
14 EVENT(PM_EXEC_STALL, 0x30008);
15 EVENT(PM_INST_CMPL, 0x500fa);
16 EVENT(PM_BR_CMPL, 0x4d05e);
17 EVENT(PM_BR_MPRED_CMPL, 0x400f6);
18 EVENT(PM_BR_FIN, 0x2f04a);
19 EVENT(PM_MPRED_BR_FIN, 0x3e098);
20 EVENT(PM_LD_DEMAND_MISS_L1_FIN, 0x400f0);
23 EVENT(PM_LD_REF_L1, 0x100fc);
[all …]
H A Dpower8-events-list.h11 EVENT(PM_CYC, 0x0001e)
12 EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
13 EVENT(PM_CMPLU_STALL, 0x4000a)
14 EVENT(PM_INST_CMPL, 0x00002)
15 EVENT(PM_BRU_FIN, 0x10068)
16 EVENT(PM_BR_MPRED_CMPL, 0x400f6)
19 EVENT(PM_LD_REF_L1, 0x100ee)
21 EVENT(PM_LD_MISS_L1, 0x3e054)
23 EVENT(PM_ST_MISS_L1, 0x300f0)
25 EVENT(PM_L1_PREF, 0x0d8b8)
[all …]
H A Dpower9-events-list.h11 EVENT(PM_CYC, 0x0001e)
12 EVENT(PM_ICT_NOSLOT_CYC, 0x100f8)
13 EVENT(PM_CMPLU_STALL, 0x1e054)
14 EVENT(PM_INST_CMPL, 0x00002)
15 EVENT(PM_BR_CMPL, 0x4d05e)
16 EVENT(PM_BR_MPRED_CMPL, 0x400f6)
19 EVENT(PM_LD_REF_L1, 0x100fc)
21 EVENT(PM_LD_MISS_L1_FIN, 0x2c04e)
22 EVENT(PM_LD_MISS_L1, 0x3e054)
24 EVENT(PM_LD_MISS_L1_ALT, 0x400f0)
[all …]
/openbmc/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-85xx.h12 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
20 #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
21 #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
22 #define _PAGE_RW 0x00004 /* S: Write permission (SW) */
23 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */
24 #define _PAGE_EXEC 0x00010 /* H: SX permission */
25 #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
27 #define _PAGE_ENDIAN 0x00040 /* H: E bit */
28 #define _PAGE_GUARDED 0x00080 /* H: G bit */
29 #define _PAGE_COHERENT 0x00100 /* H: M bit */
[all …]
/openbmc/linux/arch/powerpc/include/uapi/asm/
H A Dtermbits.h48 #define VINTR 0
67 #define IXON 0x0200
68 #define IXOFF 0x0400
69 #define IUCLC 0x1000
70 #define IMAXBEL 0x2000
71 #define IUTF8 0x4000
74 #define ONLCR 0x00002
75 #define OLCUC 0x00004
76 #define NLDLY 0x00300
77 #define NL0 0x00000
[all …]
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-g-audio.rst57 :header-rows: 0
58 :stub-columns: 0
87 :header-rows: 0
88 :stub-columns: 0
92 - 0x00001
98 - 0x00002
107 :header-rows: 0
108 :stub-columns: 0
112 - 0x00001
118 On success 0 is returned, on error -1 and the ``errno`` variable is set
/openbmc/linux/arch/alpha/include/uapi/asm/
H A Dtermbits.h54 #define VEOF 0
73 #define IXON 0x0200
74 #define IXOFF 0x0400
75 #define IUCLC 0x1000
76 #define IMAXBEL 0x2000
77 #define IUTF8 0x4000
80 #define ONLCR 0x00002
81 #define OLCUC 0x00004
82 #define NLDLY 0x00300
83 #define NL0 0x00000
[all …]
/openbmc/qemu/target/ppc/
H A Dmmu-hash64.h27 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
28 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
34 #define SLB_VSID_B 0xc000000000000000ULL
35 #define SLB_VSID_B_256M 0x0000000000000000ULL
36 #define SLB_VSID_B_1T 0x4000000000000000ULL
37 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
38 #define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
40 #define SLB_VSID_KS 0x0000000000000800ULL
41 #define SLB_VSID_KP 0x0000000000000400ULL
42 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
[all …]
/openbmc/linux/arch/sparc/include/uapi/asm/
H A Dtermbits.h51 #define VINTR 0
78 #define IUCLC 0x0200
79 #define IXON 0x0400
80 #define IXOFF 0x1000
81 #define IMAXBEL 0x2000
82 #define IUTF8 0x4000
85 #define OLCUC 0x00002
86 #define ONLCR 0x00004
87 #define NLDLY 0x00100
88 #define NL0 0x00000
[all …]
/openbmc/linux/Documentation/admin-guide/perf/
H A Dhns3-pmu.rst44 config=0x00204
46 config=0x10204
51 The bits 0~15 of config (here 0x0204) are the true hardware event code. If
52 two events have same value of bits 0~15 of config, that means they are
53 event pair. And the bit 16 of config indicates getting counter 0 or
59 counter 0 / counter 1
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
90 is same as mac id. The "tc" filter option must be set to 0xF in this mode,
95 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000
[all …]
/openbmc/qemu/target/arm/
H A Dkvm-consts.h26 #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
30 #define CP_REG_SIZE_MASK 0x00f0000000000000ULL
31 #define CP_REG_SIZE_U32 0x0020000000000000ULL
32 #define CP_REG_SIZE_U64 0x0030000000000000ULL
33 #define CP_REG_ARM 0x4000000000000000ULL
34 #define CP_REG_ARCH_MASK 0xff00000000000000ULL
43 #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
45 #define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0)
55 #define QEMU_PSCI_0_2_FN_BASE 0x84000000
58 #define QEMU_PSCI_0_2_64BIT 0x40000000
[all …]
/openbmc/linux/include/linux/perf/
H A Darm_pmu.h27 #define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */
28 #define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */
29 #define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */
35 #define HW_OP_UNSUPPORTED 0xFFFF
37 #define CACHE_OP_UNSUPPORTED 0xFFFF
40 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
43 [0 ... C(MAX) - 1] = { \
44 [0 ... C(OP_MAX) - 1] = { \
45 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
58 * an event. A 0 means that the counter can be used.
[all …]
/openbmc/u-boot/include/asm-generic/
H A Dglobal_data.h142 #define gd_board_type() 0
148 #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
149 #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
150 #define GD_FLG_SILENT 0x00004 /* Silent mode */
151 #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
152 #define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
153 #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
154 #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
155 #define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
156 #define GD_FLG_SERIAL_READY 0x00100 /* Pre-reloc serial console ready */
[all …]
/openbmc/linux/drivers/scsi/megaraid/
H A Dmegaraid_ioctl.h25 #define CL_ANN 0 /* print unconditionally, announcements */
46 #define MEGAIOCCMD _IOWR(MEGAIOC_MAGIC, 0, mimd_t)
52 #define USCSICMD 0x80
53 #define UIOC_RD 0x00001
54 #define UIOC_WR 0x00002
56 #define MBOX_CMD 0x00000
57 #define GET_DRIVER_VER 0x10000
58 #define GET_N_ADAP 0x20000
59 #define GET_ADAP_INFO 0x30000
60 #define GET_CAP 0x40000
[all …]
/openbmc/linux/drivers/usb/gadget/udc/
H A Dgoku_udc.h12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
[all …]
/openbmc/linux/lib/
H A Dkunit_iov_iter.c26 { 0x00002, 0x00002 },
27 { 0x00027, 0x03000 },
28 { 0x05193, 0x18794 },
29 { 0x20000, 0x20000 },
30 { 0x20000, 0x24000 },
31 { 0x24000, 0x27001 },
32 { 0x29000, 0xffffb },
33 { 0xffffd, 0xffffe },
39 return x & 0xff; in pattern()
78 size_t size = 0; in iov_kunit_load_kvec()
[all …]
/openbmc/linux/drivers/scsi/ibmvscsi_tgt/
H A Dibmvscsi_tgt.h27 #define MSG_HI 0
36 #define SRP_VIOLATION 0x102 /* general error code */
55 #define LOCAL 0
70 #define ADAPT_SUCCESS 0L
139 SCSI_CDB = 0x01,
140 TASK_MANAGEMENT = 0x02,
141 /* MAD or addressed to port 0 */
142 ADAPTER_MAD = 0x04,
143 UNSET_TYPE = 0x08,
166 #define CMD_FAST_FAIL BIT(0)
[all …]

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