Lines Matching +full:0 +full:x00002

26 #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
30 #define CP_REG_SIZE_MASK       0x00f0000000000000ULL
31 #define CP_REG_SIZE_U32        0x0020000000000000ULL
32 #define CP_REG_SIZE_U64        0x0030000000000000ULL
33 #define CP_REG_ARM             0x4000000000000000ULL
34 #define CP_REG_ARCH_MASK       0xff00000000000000ULL
43 #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
45 #define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0)
55 #define QEMU_PSCI_0_2_FN_BASE 0x84000000
58 #define QEMU_PSCI_0_2_64BIT 0x40000000
63 #define QEMU_PSCI_0_2_FN_PSCI_VERSION QEMU_PSCI_0_2_FN(0)
96 #define QEMU_PSCI_VERSION_0_1                     0x00001
97 #define QEMU_PSCI_VERSION_0_2                     0x00002
98 #define QEMU_PSCI_VERSION_1_0                     0x10000
99 #define QEMU_PSCI_VERSION_1_1                     0x10001
103 MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2));
107 #define QEMU_PSCI_RET_SUCCESS                     0
131 #define QEMU_KVM_ARM_TARGET_AEM_V8 0
148 #define CP_REG_ARM64                   0x6000000000000000ULL
149 #define CP_REG_ARM_COPROC_MASK         0x000000000FFF0000
151 #define CP_REG_ARM64_SYSREG            (0x0013 << CP_REG_ARM_COPROC_SHIFT)
152 #define CP_REG_ARM64_SYSREG_OP0_MASK   0x000000000000c000
154 #define CP_REG_ARM64_SYSREG_OP1_MASK   0x0000000000003800
156 #define CP_REG_ARM64_SYSREG_CRN_MASK   0x0000000000000780
158 #define CP_REG_ARM64_SYSREG_CRM_MASK   0x0000000000000078
160 #define CP_REG_ARM64_SYSREG_OP2_MASK   0x0000000000000007
161 #define CP_REG_ARM64_SYSREG_OP2_SHIFT  0