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/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-g-audio.rst57 :header-rows: 0
58 :stub-columns: 0
87 :header-rows: 0
88 :stub-columns: 0
92 - 0x00001
98 - 0x00002
107 :header-rows: 0
108 :stub-columns: 0
112 - 0x00001
118 On success 0 is returned, on error -1 and the ``errno`` variable is set
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/openbmc/linux/arch/x86/events/
H A Dperf_event_flags.h5 PERF_ARCH(PEBS_LDLAT, 0x00001) /* ld+ldlat data address sampling */
6 PERF_ARCH(PEBS_ST, 0x00002) /* st data address sampling */
7 PERF_ARCH(PEBS_ST_HSW, 0x00004) /* haswell style datala, store */
8 PERF_ARCH(PEBS_LD_HSW, 0x00008) /* haswell style datala, load */
9 PERF_ARCH(PEBS_NA_HSW, 0x00010) /* haswell style datala, unknown */
10 PERF_ARCH(EXCL, 0x00020) /* HT exclusivity on counter */
11 PERF_ARCH(DYNAMIC, 0x00040) /* dynamic alloc'd constraint */
12 /* 0x00080 */
13 PERF_ARCH(EXCL_ACCT, 0x00100) /* accounted EXCL event */
14 PERF_ARCH(AUTO_RELOAD, 0x00200) /* use PEBS auto-reload */
[all …]
/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_dpcd.h16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Ddp.h12 #define DPCD_RC00_DPCD_REV 0x00000
13 #define DPCD_RC01_MAX_LINK_RATE 0x00001
14 #define DPCD_RC02 0x00002
15 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80
16 #define DPCD_RC02_TPS3_SUPPORTED 0x40
17 #define DPCD_RC02_MAX_LANE_COUNT 0x1f
18 #define DPCD_RC03 0x00003
19 #define DPCD_RC03_TPS4_SUPPORTED 0x80
20 #define DPCD_RC03_MAX_DOWNSPREAD 0x01
21 #define DPCD_RC0E 0x0000e
[all …]
/openbmc/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-85xx.h12 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR
20 #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
21 #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
22 #define _PAGE_RW 0x00004 /* S: Write permission (SW) */
23 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */
24 #define _PAGE_EXEC 0x00010 /* H: SX permission */
25 #define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
27 #define _PAGE_ENDIAN 0x00040 /* H: E bit */
28 #define _PAGE_GUARDED 0x00080 /* H: G bit */
29 #define _PAGE_COHERENT 0x00100 /* H: M bit */
[all …]
/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x4000
65 #define IUTF8 0x8000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/linux/include/uapi/asm-generic/
H A Dtermbits.h42 #define VINTR 0
61 #define IUCLC 0x0200
62 #define IXON 0x0400
63 #define IXOFF 0x1000
64 #define IMAXBEL 0x2000
65 #define IUTF8 0x4000
68 #define OLCUC 0x00002
69 #define ONLCR 0x00004
70 #define NLDLY 0x00100
71 #define NL0 0x00000
[all …]
/openbmc/qemu/target/ppc/
H A Dmmu-hash64.h27 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
28 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
34 #define SLB_VSID_B 0xc000000000000000ULL
35 #define SLB_VSID_B_256M 0x0000000000000000ULL
36 #define SLB_VSID_B_1T 0x4000000000000000ULL
37 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
38 #define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
40 #define SLB_VSID_KS 0x0000000000000800ULL
41 #define SLB_VSID_KP 0x0000000000000400ULL
42 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
[all …]
/openbmc/qemu/target/arm/
H A Dkvm-consts.h26 #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
30 #define CP_REG_SIZE_MASK 0x00f0000000000000ULL
31 #define CP_REG_SIZE_U32 0x0020000000000000ULL
32 #define CP_REG_SIZE_U64 0x0030000000000000ULL
33 #define CP_REG_ARM 0x4000000000000000ULL
34 #define CP_REG_ARCH_MASK 0xff00000000000000ULL
43 #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e
45 #define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0)
55 #define QEMU_PSCI_0_2_FN_BASE 0x84000000
58 #define QEMU_PSCI_0_2_64BIT 0x40000000
[all …]
/openbmc/linux/include/linux/perf/
H A Darm_pmu.h27 #define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */
28 #define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */
29 #define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */
35 #define HW_OP_UNSUPPORTED 0xFFFF
37 #define CACHE_OP_UNSUPPORTED 0xFFFF
40 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
43 [0 ... C(MAX) - 1] = { \
44 [0 ... C(OP_MAX) - 1] = { \
45 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
58 * an event. A 0 means that the counter can be used.
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
[all …]
/openbmc/u-boot/include/asm-generic/
H A Dglobal_data.h142 #define gd_board_type() 0
148 #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
149 #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
150 #define GD_FLG_SILENT 0x00004 /* Silent mode */
151 #define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
152 #define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
153 #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
154 #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
155 #define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
156 #define GD_FLG_SERIAL_READY 0x00100 /* Pre-reloc serial console ready */
[all …]
/openbmc/linux/arch/mips/include/uapi/asm/
H A Dtermbits.h55 #define VINTR 0 /* Interrupt character [ISIG] */
67 #if 0
81 #define IUCLC 0x0200 /* Map upper case to lower case on input */
82 #define IXON 0x0400 /* Enable start/stop output control */
83 #define IXOFF 0x1000 /* Enable start/stop input control */
84 #define IMAXBEL 0x2000 /* Ring bell when input queue is full */
85 #define IUTF8 0x4000 /* Input is UTF-8 */
88 #define OLCUC 0x00002 /* Map lower case to upper case on output */
89 #define ONLCR 0x00004 /* Map NL to CR-NL on output */
90 #define NLDLY 0x00100
[all …]
/openbmc/linux/drivers/scsi/megaraid/
H A Dmegaraid_ioctl.h25 #define CL_ANN 0 /* print unconditionally, announcements */
46 #define MEGAIOCCMD _IOWR(MEGAIOC_MAGIC, 0, mimd_t)
52 #define USCSICMD 0x80
53 #define UIOC_RD 0x00001
54 #define UIOC_WR 0x00002
56 #define MBOX_CMD 0x00000
57 #define GET_DRIVER_VER 0x10000
58 #define GET_N_ADAP 0x20000
59 #define GET_ADAP_INFO 0x30000
60 #define GET_CAP 0x40000
[all …]
/openbmc/linux/drivers/usb/gadget/udc/
H A Dgoku_udc.h12 * PCI BAR 0 points to these registers.
16 u32 int_status; /* 0x000 */
18 #define INT_SUSPEND 0x00001 /* or resume */
19 #define INT_USBRESET 0x00002
20 #define INT_ENDPOINT0 0x00004
21 #define INT_SETUP 0x00008
22 #define INT_STATUS 0x00010
23 #define INT_STATUSNAK 0x00020
24 #define INT_EPxDATASET(n) (0x00020 << (n)) /* 0 < n < 4 */
25 # define INT_EP1DATASET 0x00040
[all …]
/openbmc/linux/drivers/scsi/aic7xxx/
H A Daic79xx.h60 #define FALSE 0
63 #define ALL_CHANNELS '\0'
64 #define ALL_TARGETS_MASK 0xFFFF
65 #define INITIATOR_WILDCARD (~0)
66 #define SCB_LIST_NULL 0xFF00
68 #define QOUTFIFO_ENTRY_VALID 0x80
69 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
76 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
88 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
91 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800pci.c60 for (i = 0; i < 200; i++) { in rt2800pci_mcu_status()
75 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); in rt2800pci_mcu_status()
76 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); in rt2800pci_mcu_status()
97 u32 reg = 0; in rt2800pci_eepromregister_write()
121 case 0: in rt2800pci_read_eeprom_pci()
131 eeprom.reg_data_in = 0; in rt2800pci_read_eeprom_pci()
132 eeprom.reg_data_out = 0; in rt2800pci_read_eeprom_pci()
133 eeprom.reg_data_clock = 0; in rt2800pci_read_eeprom_pci()
134 eeprom.reg_chip_select = 0; in rt2800pci_read_eeprom_pci()
139 return 0; in rt2800pci_read_eeprom_pci()
[all …]
/openbmc/linux/include/uapi/linux/
H A Dmedia.h48 #define MEDIA_ENT_F_BASE 0x00000000
49 #define MEDIA_ENT_F_OLD_BASE 0x00010000
50 #define MEDIA_ENT_F_OLD_SUBDEV_BASE 0x00020000
68 #define MEDIA_ENT_F_DTV_DEMOD (MEDIA_ENT_F_BASE + 0x00001)
69 #define MEDIA_ENT_F_TS_DEMUX (MEDIA_ENT_F_BASE + 0x00002)
70 #define MEDIA_ENT_F_DTV_CA (MEDIA_ENT_F_BASE + 0x00003)
71 #define MEDIA_ENT_F_DTV_NET_DECAP (MEDIA_ENT_F_BASE + 0x00004)
77 #define MEDIA_ENT_F_IO_DTV (MEDIA_ENT_F_BASE + 0x01001)
78 #define MEDIA_ENT_F_IO_VBI (MEDIA_ENT_F_BASE + 0x01002)
79 #define MEDIA_ENT_F_IO_SWRADIO (MEDIA_ENT_F_BASE + 0x01003)
[all …]
/openbmc/linux/arch/x86/include/asm/
H A Dapicdef.h14 #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
15 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
23 #define APIC_ID 0x20
25 #define APIC_LVR 0x30
26 #define APIC_LVR_MASK 0xFF00FF
28 #define GET_APIC_VERSION(x) ((x) & 0xFFu)
29 #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
31 # define APIC_INTEGRATED(x) ((x) & 0xF0u)
35 #define APIC_XAPIC(x) ((x) >= 0x14)
36 #define APIC_EXT_SPACE(x) ((x) & 0x80000000)
[all …]
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcpu.c49 case 0x00001: in get_reset_cause()
50 case 0x00011: in get_reset_cause()
52 case 0x00004: in get_reset_cause()
54 case 0x00008: in get_reset_cause()
56 case 0x00010: in get_reset_cause()
62 case 0x00020: in get_reset_cause()
64 case 0x00040: in get_reset_cause()
66 case 0x00080: in get_reset_cause()
69 case 0x00100: in get_reset_cause()
71 case 0x00200: in get_reset_cause()
[all …]
/openbmc/qemu/hw/dma/
H A Dpl080.c21 #define PL080_CONF_E 0x1
22 #define PL080_CONF_M1 0x2
23 #define PL080_CONF_M2 0x4
25 #define PL080_CCONF_H 0x40000
26 #define PL080_CCONF_A 0x20000
27 #define PL080_CCONF_L 0x10000
28 #define PL080_CCONF_ITC 0x08000
29 #define PL080_CCONF_IE 0x04000
30 #define PL080_CCONF_E 0x00001
32 #define PL080_CCTRL_I 0x80000000
[all …]

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