21 #define PL080_CONF_E    0x1
22 #define PL080_CONF_M1   0x2
23 #define PL080_CONF_M2   0x4
25 #define PL080_CCONF_H   0x40000
26 #define PL080_CCONF_A   0x20000
27 #define PL080_CCONF_L   0x10000
28 #define PL080_CCONF_ITC 0x08000
29 #define PL080_CCONF_IE  0x04000
30 #define PL080_CCONF_E   0x00001
32 #define PL080_CCTRL_I   0x80000000
33 #define PL080_CCTRL_DI  0x08000000
34 #define PL080_CCTRL_SI  0x04000000
35 #define PL080_CCTRL_D   0x02000000
36 #define PL080_CCTRL_S   0x01000000
76 { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
79 { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
106     s->tc_mask = 0;  in pl080_run()
107     for (c = 0; c < s->nchannels; c++) {  in pl080_run()
114     if ((s->conf & PL080_CONF_E) == 0)  in pl080_run()
125         for (c = 0; c < s->nchannels; c++) {  in pl080_run()
137             src_id = (ch->conf >> 1) & 0x1f;  in pl080_run()
138             dest_id = (ch->conf >> 6) & 0x1f;  in pl080_run()
139             size = ch->ctrl & 0xfff;  in pl080_run()
142             case 0:  in pl080_run()
145                 if ((req & (1u << dest_id)) == 0)  in pl080_run()
146                     size = 0;  in pl080_run()
149                 if ((req & (1u << src_id)) == 0)  in pl080_run()
150                     size = 0;  in pl080_run()
153                 if ((req & (1u << src_id)) == 0  in pl080_run()
154                         || (req & (1u << dest_id)) == 0)  in pl080_run()
155                     size = 0;  in pl080_run()
167             for (n = 0; n < dwidth; n+= swidth) {  in pl080_run()
175             for (n = 0; n < xsize; n += dwidth) {  in pl080_run()
183             ch->ctrl = (ch->ctrl & 0xfffff000) | size;  in pl080_run()
184             if (size == 0) {  in pl080_run()
224     if (offset >= 0xfe0 && offset < 0x1000) {  in pl080_read()
226             return pl080_id[(offset - 0xfe0) >> 2];  in pl080_read()
228             return pl081_id[(offset - 0xfe0) >> 2];  in pl080_read()
231     if (offset >= 0x100 && offset < 0x200) {  in pl080_read()
232         i = (offset & 0xe0) >> 5;  in pl080_read()
236         case 0: /* SrcAddr */  in pl080_read()
251     case 0: /* IntStatus */  in pl080_read()
262         mask = 0;  in pl080_read()
263         for (i = 0; i < s->nchannels; i++) {  in pl080_read()
273         return 0;  in pl080_read()
282         return 0;  in pl080_read()
292     if (offset >= 0x100 && offset < 0x200) {  in pl080_write()
293         i = (offset & 0xe0) >> 5;  in pl080_write()
297         case 0: /* SrcAddr */  in pl080_write()
360     s->tc_int = 0;  in pl080_reset()
361     s->tc_mask = 0;  in pl080_reset()
362     s->err_int = 0;  in pl080_reset()
363     s->err_mask = 0;  in pl080_reset()
364     s->conf = 0;  in pl080_reset()
365     s->sync = 0;  in pl080_reset()
366     s->req_single = 0;  in pl080_reset()
367     s->req_burst = 0;  in pl080_reset()
368     s->running = 0;  in pl080_reset()
370     for (i = 0; i < s->nchannels; i++) {  in pl080_reset()
371         s->chan[i].src = 0;  in pl080_reset()
372         s->chan[i].dest = 0;  in pl080_reset()
373         s->chan[i].lli = 0;  in pl080_reset()
374         s->chan[i].ctrl = 0;  in pl080_reset()
375         s->chan[i].conf = 0;  in pl080_reset()
384     memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);  in pl080_init()