| /openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
| H A D | lcd.h | 14 u32 ssar; /* 0x00 Screen Start Address Register */
15 u32 sr; /* 0x04 LCD Size Register */
16 u32 vpw; /* 0x08 Virtual Page Width Register */
17 u32 cpr; /* 0x0C Cursor Position Register */
18 u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
19 u32 ccmr; /* 0x14 Color Cursor Mapping Register */
20 u32 pcr; /* 0x18 Panel Configuration Register */
21 u32 hcr; /* 0x1C Horizontal Configuration Register */
22 u32 vcr; /* 0x20 Vertical Configuration Register */
23 u32 por; /* 0x24 Panning Offset Register */
[all …]
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| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | rtc.h | 14 u32 hourmin; /* 0x00 Hours and Minutes Counter Register */
15 u32 seconds; /* 0x04 Seconds Counter Register */
16 u32 alrm_hm; /* 0x08 Hours and Minutes Alarm Register */
17 u32 alrm_sec; /* 0x0C Seconds Alarm Register */
18 u32 cr; /* 0x10 Control Register */
19 u32 isr; /* 0x14 Interrupt Status Register */
20 u32 ier; /* 0x18 Interrupt Enable Register */
21 u32 stpwatch; /* 0x1C Stopwatch Minutes Register */
22 u32 days; /* 0x20 Days Counter Register */
23 u32 alrm_day; /* 0x24 Days Alarm Register */
[all …]
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| /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | sdram_arria10.h | 210 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
212 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
214 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
216 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
218 #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
220 #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
222 #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
223 #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
231 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
245 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
[all …]
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| H A D | clock_manager_arria10.h | 103 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
104 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
109 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
110 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
111 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
112 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
113 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
114 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
115 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
116 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
[all …]
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| /openbmc/linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra124-nyan-blaze-emc.dtsi | 92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
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| H A D | tegra124-jetson-tk1-emc.dtsi | 104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
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| H A D | tegra124-apalis-emc.dtsi | 108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
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| H A D | tegra124-nyan-big-emc.dtsi | 263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
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| /openbmc/linux/include/sound/ |
| H A D | cs35l56.h | 16 #define CS35L56_DEVID 0x0000000
17 #define CS35L56_REVID 0x0000004
18 #define CS35L56_RELID 0x000000C
19 #define CS35L56_OTPID 0x0000010
20 #define CS35L56_SFT_RESET 0x0000020
21 #define CS35L56_GLOBAL_ENABLES 0x0002014
22 #define CS35L56_BLOCK_ENABLES 0x0002018
23 #define CS35L56_BLOCK_ENABLES2 0x000201C
24 #define CS35L56_REFCLK_INPUT 0x0002C04
25 #define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C
[all …]
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | powernow-k8.h | 43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
[all …]
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| /openbmc/u-boot/board/kmc/kzm9g/ |
| H A D | kzm9g.c | 16 #define CS0BCR_D (0x06C00400)
17 #define CS4BCR_D (0x16c90400)
18 #define CS0WCR_D (0x55062C42)
19 #define CS4WCR_D (0x1e071dc3)
24 #define VCLKCR1_D (0x27)
31 #define PORT32CR (0xE6051020)
32 #define PORT33CR (0xE6051021)
33 #define PORT34CR (0xE6051022)
34 #define PORT35CR (0xE6051023)
42 while (timeout > 0) { in cmp_loop()
[all …]
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| /openbmc/linux/include/linux/ssb/ |
| H A D | ssb_driver_extif.h | 24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
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| /openbmc/qemu/include/hw/usb/ |
| H A D | ehci-regs.h | 5 #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
6 #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
7 #define HCSPARAMS 0x0004 /* 4-bytes, structural params */
8 #define HCCPARAMS 0x0008 /* 4-bytes, capability params */
10 #define HCSPPORTROUTE1 0x000c
11 #define HCSPPORTROUTE2 0x0010
13 #define USBCMD 0x0000
14 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
24 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
27 #define USBSTS 0x0004
[all …]
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| /openbmc/linux/drivers/media/rc/img-ir/ |
| H A D | img-ir.h | 20 #define IMG_IR_CONTROL 0x00
21 #define IMG_IR_STATUS 0x04
22 #define IMG_IR_DATA_LW 0x08
23 #define IMG_IR_DATA_UP 0x0c
24 #define IMG_IR_LEAD_SYMB_TIMING 0x10
25 #define IMG_IR_S00_SYMB_TIMING 0x14
26 #define IMG_IR_S01_SYMB_TIMING 0x18
27 #define IMG_IR_S10_SYMB_TIMING 0x1c
28 #define IMG_IR_S11_SYMB_TIMING 0x20
29 #define IMG_IR_FREE_SYMB_TIMING 0x24
[all …]
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| /openbmc/linux/arch/powerpc/include/asm/nohash/32/ |
| H A D | mmu-44x.h | 10 #define PPC44x_MMUCR_TID 0x000000ff
11 #define PPC44x_MMUCR_STS 0x00010000
13 #define PPC44x_TLB_PAGEID 0
18 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
19 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
20 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
21 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
22 #define PPC44x_TLB_4K 0x00000010
23 #define PPC44x_TLB_16K 0x00000020
24 #define PPC44x_TLB_64K 0x00000030
[all …]
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/privring/ |
| H A D | gk104.c | 31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); in gk104_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); in gk104_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); in gk104_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); in gk104_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); in gk104_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); in gk104_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); in gk104_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); in gk104_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); in gk104_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x120058); in gk104_privring_intr()
[all …]
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| H A D | gf100.c | 31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); in gf100_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x121c58); in gf100_privring_intr()
[all …]
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| /openbmc/linux/include/linux/bcma/ |
| H A D | bcma_driver_mips.h | 5 #define BCMA_MIPS_IPSFLAG 0x0F08
7 #define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
8 #define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
10 #define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
13 #define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
16 #define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
20 #define BCMA_MIPS_MIPS74K_CORECTL 0x0000
21 #define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
22 #define BCMA_MIPS_MIPS74K_BIST 0x000C
23 #define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | clock.h | 19 #define FCK_IVA2_ON 0x00000001
20 #define FCK_CORE1_ON 0x03fffe29
21 #define ICK_CORE1_ON 0x3ffffffb
22 #define ICK_CORE2_ON 0x0000001f
23 #define FCK_WKUP_ON 0x000000e9
24 #define ICK_WKUP_ON 0x0000003f
25 #define FCK_DSS_ON 0x00000005
26 #define ICK_DSS_ON 0x00000001
27 #define FCK_CAM_ON 0x00000001
28 #define ICK_CAM_ON 0x00000001
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| /openbmc/u-boot/drivers/video/ |
| H A D | ati_radeon_fb.h | 97 for (i=0; i < 2000000; i++) { in radeon_engine_flush()
109 for (i=0; i<2000000; i++) { in _radeon_fifo_wait()
110 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()
124 for (i=0; i<2000000; i++) { in _radeon_engine_idle()
125 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()
250 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); in __INPLL()
261 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); in __OUTPLL()
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| /openbmc/linux/drivers/gpu/drm/i915/pxp/ |
| H A D | intel_pxp_cmd_interface_43.h | 13 #define PXP43_CMDID_START_HUC_AUTH 0x0000003A
14 #define PXP43_CMDID_NEW_HUC_AUTH 0x0000003F /* MTL+ */
15 #define PXP43_CMDID_INIT_SESSION 0x00000036
45 #define PXP43_INIT_SESSION_VALID BIT(0)
49 #define PXP43_INIT_SESSION_PROTECTION_ARB 0x2
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | rk3399-sdram-ddr3-1866.dtsi | 8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80181219
18 0x17050a03
[all …]
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| H A D | rk3399-sdram-ddr3-1333.dtsi | 8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80120e12
18 0x11030802
[all …]
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| H A D | rk3399-sdram-ddr3-1600.dtsi | 8 0x1
9 0xa
10 0x3
11 0x2
12 0x1
13 0x0
14 0xf
15 0xf
17 0x80151015
18 0x14040902
[all …]
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| /openbmc/u-boot/arch/xtensa/include/asm/ |
| H A D | regs.h | 23 #define EXCCAUSE_EXCCAUSE_SHIFT 0
24 #define EXCCAUSE_EXCCAUSE_MASK 0x3F
26 #define EXCCAUSE_ILLEGAL_INSTRUCTION 0
65 #define PS_CALLINC_MASK 0x00030000
67 #define PS_OWB_MASK 0x00000F00
69 #define PS_RING_MASK 0x000000C0
72 #define PS_INTLEVEL_SHIFT 0
73 #define PS_INTLEVEL_MASK 0x0000000F
77 #define DBREAKC_MASK_BIT 0
78 #define DBREAKC_MASK_MASK 0x0000003F
[all …]
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