Lines Matching +full:0 +full:x0000003f
16 #define CS0BCR_D (0x06C00400)
17 #define CS4BCR_D (0x16c90400)
18 #define CS0WCR_D (0x55062C42)
19 #define CS4WCR_D (0x1e071dc3)
24 #define VCLKCR1_D (0x27)
31 #define PORT32CR (0xE6051020)
32 #define PORT33CR (0xE6051021)
33 #define PORT34CR (0xE6051022)
34 #define PORT35CR (0xE6051023)
42 while (timeout > 0) { in cmp_loop()
45 err = 0; in cmp_loop()
57 writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); in sbsc_init()
58 writel(0x5, &sbsc->sdgencnt); in sbsc_init()
59 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); in sbsc_init()
61 writel(0xacc90159, &sbsc->sdcr0); in sbsc_init()
62 writel(0x00010059, &sbsc->sdcr1); in sbsc_init()
63 writel(0x50874114, &sbsc->sdwcrc0); in sbsc_init()
64 writel(0x33199b37, &sbsc->sdwcrc1); in sbsc_init()
65 writel(0x008f2313, &sbsc->sdwcrc2); in sbsc_init()
66 writel(0x31020707, &sbsc->sdwcr00); in sbsc_init()
67 writel(0x0017040a, &sbsc->sdwcr01); in sbsc_init()
68 writel(0x31020707, &sbsc->sdwcr10); in sbsc_init()
69 writel(0x0017040a, &sbsc->sdwcr11); in sbsc_init()
70 writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */ in sbsc_init()
71 writel(0x30000000, &sbsc->sdwcr2); in sbsc_init()
73 writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); in sbsc_init()
74 cmp_loop(&sbsc->sdpcr, 0x80, 0x80); in sbsc_init()
76 writel(0x00002710, &sbsc->sdgencnt); in sbsc_init()
77 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); in sbsc_init()
79 writel(0x0000003f, &sbsc->sdmracr0); in sbsc_init()
80 writel(0x0, SDMRA1A); in sbsc_init()
81 writel(0x000001f4, &sbsc->sdgencnt); in sbsc_init()
82 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); in sbsc_init()
84 writel(0x0000ff0a, &sbsc->sdmracr0); in sbsc_init()
86 writel(0x0, SDMRA3A); in sbsc_init()
88 writel(0x0, SDMRA3B); in sbsc_init()
90 writel(0x00000032, &sbsc->sdgencnt); in sbsc_init()
91 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); in sbsc_init()
94 writel(0x00002201, &sbsc->sdmracr0); in sbsc_init()
95 writel(0x0, SDMRA1A); in sbsc_init()
96 writel(0x00000402, &sbsc->sdmracr0); in sbsc_init()
97 writel(0x0, SDMRA1A); in sbsc_init()
98 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ in sbsc_init()
99 writel(0x0, SDMRA1A); in sbsc_init()
100 writel(0x0, SDMRA2A); in sbsc_init()
102 writel(0x00002201, &sbsc->sdmracr0); in sbsc_init()
103 writel(0x0, SDMRA1B); in sbsc_init()
104 writel(0x00000402, &sbsc->sdmracr0); in sbsc_init()
105 writel(0x0, SDMRA1B); in sbsc_init()
106 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ in sbsc_init()
107 writel(0x0, SDMRA1B); in sbsc_init()
108 writel(0x0, SDMRA2B); in sbsc_init()
111 writel(0x88800004, &sbsc->sdmrtmpcr); in sbsc_init()
112 writel(0x00000004, &sbsc->sdmrtmpmsk); in sbsc_init()
113 writel(0xa55a0032, &sbsc->rtcor); in sbsc_init()
114 writel(0xa55a000c, &sbsc->rtcorh); in sbsc_init()
115 writel(0xa55a2048, &sbsc->rtcsr); in sbsc_init()
116 writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); in sbsc_init()
117 writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); in sbsc_init()
118 writel(0xfff20000, &sbsc->zqccr); in sbsc_init()
122 writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); in sbsc_init()
123 writel(0xa5390000, &sbsc->dphycnt1); in sbsc_init()
124 writel(0x00001200, &sbsc->dphycnt0); in sbsc_init()
125 writel(0x07ce0000, &sbsc->dphycnt1); in sbsc_init()
126 writel(0x00001247, &sbsc->dphycnt0); in sbsc_init()
127 cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); in sbsc_init()
128 writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); in sbsc_init()
145 writew(0xA507, &rwdt->rwtcsra0); in s_init()
155 writel(0x0, &cpg->pllecr); in s_init()
157 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); in s_init()
158 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); in s_init()
160 writel(0x2D000000, &cpg->pll0cr); in s_init()
161 writel(0x17100000, &cpg->pll1cr); in s_init()
162 writel(0x96235880, &cpg->frqcrb); in s_init()
163 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); in s_init()
165 writel(0xB, &cpg->flckcr); in s_init()
169 writel(0x0514, &hpb_bscr->smgpiotime); in s_init()
170 writel(0x0514, &hpb_bscr->smcmt2time); in s_init()
171 writel(0x0514, &hpb_bscr->smcpgtime); in s_init()
172 writel(0x0514, &hpb_bscr->smsysctime); in s_init()
174 writel(0x00092000, &cpg->dvfscr4); in s_init()
175 writel(0x000000DC, &cpg->dvfscr5); in s_init()
176 writel(0x0, &cpg->pllecr); in s_init()
177 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); in s_init()
180 writel(0x0012453C, &cpg->frqcra); in s_init()
181 writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */ in s_init()
182 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); in s_init()
183 writel(0x00000B0B, &cpg->frqcrd); in s_init()
184 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); in s_init()
187 writel(0x00000003, PCLKCR); in s_init()
188 writel(0x0000012F, &cpg->vclkcr1); in s_init()
189 writel(0x00000119, &cpg->vclkcr2); in s_init()
190 writel(0x00000119, &cpg->vclkcr3); in s_init()
191 writel(0x00000002, &cpg->zbckcr); in s_init()
192 writel(0x00000005, &cpg->flckcr); in s_init()
193 writel(0x00000080, &cpg->sd0ckcr); in s_init()
194 writel(0x00000080, &cpg->sd1ckcr); in s_init()
195 writel(0x00000080, &cpg->sd2ckcr); in s_init()
196 writel(0x0000003F, &cpg->fsiackcr); in s_init()
197 writel(0x0000003F, &cpg->fsibckcr); in s_init()
198 writel(0x00000080, &cpg->subckcr); in s_init()
199 writel(0x0000000B, &cpg->spuackcr); in s_init()
200 writel(0x0000000B, &cpg->spuvckcr); in s_init()
201 writel(0x0000013F, &cpg->msuckcr); in s_init()
202 writel(0x00000080, &cpg->hsickcr); in s_init()
203 writel(0x0000003F, &cpg->mfck1cr); in s_init()
204 writel(0x0000003F, &cpg->mfck2cr); in s_init()
205 writel(0x00000107, &cpg->dsitckcr); in s_init()
206 writel(0x00000313, &cpg->dsi0pckcr); in s_init()
207 writel(0x0000130D, &cpg->dsi1pckcr); in s_init()
208 writel(0x2A800E0E, &cpg->dsi0phycr); in s_init()
209 writel(0x1E000000, &cpg->pll0cr); in s_init()
210 writel(0x2D000000, &cpg->pll0cr); in s_init()
211 writel(0x17100000, &cpg->pll1cr); in s_init()
212 writel(0x27000080, &cpg->pll2cr); in s_init()
213 writel(0x1D000000, &cpg->pll3cr); in s_init()
214 writel(0x00080000, &cpg->pll0stpcr); in s_init()
215 writel(0x000120C0, &cpg->pll1stpcr); in s_init()
216 writel(0x00012000, &cpg->pll2stpcr); in s_init()
217 writel(0x00000030, &cpg->pll3stpcr); in s_init()
219 writel(0x0000000B, &cpg->pllecr); in s_init()
220 cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); in s_init()
222 writel(0x000120F0, &cpg->dvfscr3); in s_init()
223 writel(0x00000020, &cpg->mpmode); in s_init()
224 writel(0x0000028A, &cpg->vrefcr); in s_init()
225 writel(0xE4628087, &cpg->rmstpcr0); in s_init()
226 writel(0xFFFFFFFF, &cpg->rmstpcr1); in s_init()
227 writel(0x53FFFFFF, &cpg->rmstpcr2); in s_init()
228 writel(0xFFFFFFFF, &cpg->rmstpcr3); in s_init()
229 writel(0x00800D3D, &cpg->rmstpcr4); in s_init()
230 writel(0xFFFFF3FF, &cpg->rmstpcr5); in s_init()
231 writel(0x00000000, &cpg->smstpcr2); in s_init()
232 writel(0x00040000, &cpg_srcr->srcr2); in s_init()
235 cmp_loop(&cpg->pllecr, 0x00000800, 0x0); in s_init()
237 writel(0x00000001, &hpb->hpbctrl6); in s_init()
238 cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); in s_init()
240 writel(0x00001414, &cpg->frqcrd); in s_init()
241 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); in s_init()
243 writel(0x1d000000, &cpg->pll3cr); in s_init()
245 cmp_loop(&cpg->pllecr, 0x800, 0x800); in s_init()
253 writel(0x00000b0b, &cpg->frqcrd); in s_init()
254 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); in s_init()
255 writel(0xfffffffc, &cpg->cpgxxcs4); in s_init()
279 writeb(0x12, PORT32CR); in board_early_init_f()
280 writeb(0x22, PORT33CR); in board_early_init_f()
281 writeb(0x12, PORT34CR); in board_early_init_f()
282 writeb(0x22, PORT35CR); in board_early_init_f()
284 return 0; in board_early_init_f()
291 data = 0x35; in adjust_core_voltage()
292 i2c_set_bus_num(0); in adjust_core_voltage()
293 i2c_write(0x40, 3, 1, &data, 1); in adjust_core_voltage()
345 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); in board_init()
347 return 0; in board_init()
353 return 0; in dram_init()
358 int ret = 0; in board_eth_init()
360 ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); in board_eth_init()