Lines Matching +full:0 +full:x0000003f
210 #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
212 #define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
214 #define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
216 #define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
218 #define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
220 #define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
222 #define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
223 #define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
231 #define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
245 #define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
247 #define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK 0x0000001F
248 #define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT 0
250 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK 0x3F000000
252 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK 0x00FC0000
254 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK 0x0003F000
256 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK 0x00000FC0
258 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK 0x0000003F
259 #define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT 0
261 #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK 0x3F000000
263 #define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK 0x00FC0000
265 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK 0x0003F000
267 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK 0x00000FC0
269 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK 0x0000003F
270 #define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT 0
272 #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK 0x3F000000
274 #define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK 0x00FC0000
276 #define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK 0x0003F000
278 #define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK 0x00000FC0
280 #define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK 0x0000003F
281 #define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT 0
283 #define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK 0x3F000000
285 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK 0x00FC0000
287 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK 0x0003F000
289 #define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK 0x00000FC0
291 #define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK 0x0000003F
292 #define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT 0
294 #define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK 0xFC000000
296 #define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK 0x03FC0000
298 #define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK 0x0003F000
300 #define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK 0x00000FC0
302 #define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK 0x0000003F
303 #define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT 0
305 #define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK 0x000000FF
306 #define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT 0
308 #define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK 0x00070000
310 #define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK 0x0000C000
312 #define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK 0x00003C00
314 #define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK 0x000003E0
316 #define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK 0x0000001F
317 #define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT 0
319 #define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
321 #define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK BIT(0)
323 #define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK BIT(0)
328 #define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK BIT(0)
330 #define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK BIT(0)
334 #define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
342 #define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
345 #define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
349 #define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
354 #define ALT_NOC_FW_DDR_ADDR_MASK 0xFFFF
355 #define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK BIT(0)
363 #define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK BIT(0)
380 #define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK 0x0000003F