/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra30-asus-tf201.dts | 67 reg = <0x4d>; 82 mount-matrix = "-1", "0", "0", 83 "0", "-1", "0", 84 "0", "0", "-1"; 88 mount-matrix = "0", "-1", "0", 89 "-1", "0", "0", 90 "0", "0", "-1"; 95 mount-matrix = "1", "0", "0", 96 "0", "-1", "0", 97 "0", "0", "1"; [all …]
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H A D | tegra30-asus-tf300tg.dts | 22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>, 171 reg = <0x10>; 190 mount-matrix = "1", "0", "0", 191 "0", "-1", "0", 192 "0", "0", "-1"; 196 mount-matrix = "-1", "0", "0", 197 "0", "1", "0", 198 "0", "0", "-1"; 203 mount-matrix = "0", "-1", "0", 204 "-1", "0", "0", [all …]
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H A D | tegra30-asus-tf300t.dts | 75 reg = <0x10>; 94 mount-matrix = "0", "-1", "0", 95 "-1", "0", "0", 96 "0", "0", "-1"; 100 mount-matrix = "-1", "0", "0", 101 "0", "1", "0", 102 "0", "0", "-1"; 107 mount-matrix = "0", "-1", "0", 108 "-1", "0", "0", 109 "0", "0", "1"; [all …]
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H A D | tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 13 emc-timings-0 { 17 nvidia,emc-auto-cal-interval = <0x001fffff>; 18 nvidia,emc-mode-1 = <0x80100002>; 19 nvidia,emc-mode-2 = <0x80200018>; 20 nvidia,emc-mode-reset = <0x80000b71>; 21 nvidia,emc-zcal-cnt-long = <0x00000040>; 25 0x0000001f /* EMC_RC */ 26 0x00000069 /* EMC_RFC */ 27 0x00000017 /* EMC_RAS */ 28 0x00000007 /* EMC_RP */ [all …]
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H A D | tegra30-asus-tf700t.dts | 18 port@0 { 92 reg = <0x10>; 111 mount-matrix = "1", "0", "0", 112 "0", "-1", "0", 113 "0", "0", "-1"; 117 mount-matrix = "0", "1", "0", 118 "1", "0", "0", 119 "0", "0", "-1"; 124 mount-matrix = "0", "-1", "0", 125 "-1", "0", "0", [all …]
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H A D | tegra30-pegatron-chagall.dts | 49 reg = <0x80000000 0x40000000>; 59 alloc-ranges = <0x80000000 0x30000000>; 60 size = <0x10000000>; /* 256MiB */ 67 reg = <0xbeb00000 0x10000>; /* 64kB */ 68 console-size = <0x8000>; /* 32kB */ 69 record-size = <0x400>; /* 1kB */ 74 reg = <0xbfe00000 0x200000>; /* 2MB */ 100 pinctrl-0 = <&state_default>; 144 nvidia,lock = <0>; 145 nvidia,io-reset = <0>; [all …]
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H A D | tegra20-acer-a500-picasso.dts | 37 memory@0 { 38 reg = <0x00000000 0x40000000>; 48 reg = <0x2ffe0000 0x10000>; /* 64kB */ 49 console-size = <0x8000>; /* 32kB */ 50 record-size = <0x400>; /* 1kB */ 56 alloc-ranges = <0x30000000 0x10000000>; 57 size = <0x10000000>; /* 256MiB */ 68 port@0 { 92 pinctrl-0 = <&state_default>; 425 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; [all …]
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H A D | tegra124-nyan-blaze-emc.dtsi | 92 0x40040001 93 0x8000000a 94 0x00000001 95 0x00000001 96 0x00000002 97 0x00000000 98 0x00000002 99 0x00000001 100 0x00000002 101 0x00000008 [all …]
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H A D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 { 6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ 12 0x00020001 /* MC_EMEM_ARB_CFG */ 13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ 15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ 16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ 17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ 18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ 19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ [all …]
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/openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
H A D | crossbar.h | 16 u32 prs1; /* 0x100 Priority Register Slave 1 */ 17 u32 res1[3]; /* 0x104 - 0F */ 18 u32 crs1; /* 0x110 Control Register Slave 1 */ 19 u32 res2[187]; /* 0x114 - 0x3FF */ 21 u32 prs4; /* 0x400 Priority Register Slave 4 */ 22 u32 res3[3]; /* 0x404 - 0F */ 23 u32 crs4; /* 0x410 Control Register Slave 4 */ 24 u32 res4[123]; /* 0x414 - 0x5FF */ 26 u32 prs6; /* 0x600 Priority Register Slave 6 */ 27 u32 res5[3]; /* 0x604 - 0F */ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/ |
H A D | hw_atl2_internal.h | 21 #define HW_ATL2_MAC_UC 0U 27 #define HW_ATL2_INT_MASK (0xFFFFFFFFU) 37 #define HW_ATL2_INTR_MODER_MAX 0x1FF 38 #define HW_ATL2_INTR_MODER_MIN 0xFF 48 #define HW_ATL2_FW_SM_ACT_RSLVR 0x3U 50 #define HW_ATL2_RPF_TAG_UC_OFFSET 0x0 51 #define HW_ATL2_RPF_TAG_ALLMC_OFFSET 0x6 52 #define HW_ATL2_RPF_TAG_ET_OFFSET 0x7 53 #define HW_ATL2_RPF_TAG_VLAN_OFFSET 0xA 54 #define HW_ATL2_RPF_TAG_UNTAG_OFFSET 0xE [all …]
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/openbmc/u-boot/arch/arm/mach-omap2/omap3/ |
H A D | clock.c | 55 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed() 111 *sys_clkin_sel = 0; in get_sys_clkin_sel() 136 0x00000007, PLL_FAST_RELOCK_BYPASS); in dpll3_init_34xx() 137 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, in dpll3_init_34xx() 141 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't in dpll3_init_34xx() 147 0x001F0000, (CORE_M3X2 + 1) << 16) ; in dpll3_init_34xx() 149 0x001F0000, CORE_M3X2 << 16); in dpll3_init_34xx() 153 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx() 157 0x07FF0000, ptr->m << 16); in dpll3_init_34xx() 161 0x00007F00, ptr->n << 8); in dpll3_init_34xx() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_6_0_sh_mask.h | 26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L 27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L 29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 [all …]
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v6_0_0_pkt_open.h | 26 #define SDMA_OP_NOP 0 44 #define SDMA_SUBOP_TIMESTAMP_SET 0 47 #define SDMA_SUBOP_COPY_LINEAR 0 61 #define SDMA_SUBOP_WRITE_LINEAR 0 64 #define SDMA_SUBOP_PTEPDE_GEN 0 76 #define SDMA_OP_AQL_COPY 0 77 #define SDMA_OP_AQL_BARRIER_OR 0 80 #define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) 84 #define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) 92 #define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/ |
H A D | vega10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 NO_FORCE_REQUEST = 0x00000000, 185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 187 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 195 NO_FORCE_REQ = 0x00000000, 196 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 204 ENABLE_MEM_PWR_CTRL = 0x00000000, 205 DISABLE_MEM_PWR_CTRL = 0x00000001, 213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, [all …]
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H A D | navi10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 GATCL1_TYPE_NORMAL = 0x00000000, 185 GATCL1_TYPE_SHOOTDOWN = 0x00000001, 186 GATCL1_TYPE_BYPASS = 0x00000002, 194 UTCL1_TYPE_NORMAL = 0x00000000, 195 UTCL1_TYPE_SHOOTDOWN = 0x00000001, 196 UTCL1_TYPE_BYPASS = 0x00000002, 204 UTCL1_XNACK_SUCCESS = 0x00000000, 205 UTCL1_XNACK_RETRY = 0x00000001, 206 UTCL1_XNACK_PRT = 0x00000002, [all …]
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H A D | soc21_enum.h | 55 DSM_DATA_SEL_DISABLE = 0x00000000, 56 DSM_DATA_SEL_0 = 0x00000001, 57 DSM_DATA_SEL_1 = 0x00000002, 58 DSM_DATA_SEL_BOTH = 0x00000003, 66 DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000, 67 DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001, 68 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002, 69 DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003, 77 DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000, 78 DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001, [all …]
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/openbmc/linux/arch/mips/pic32/pic32mzda/ |
H A D | early_clk.c | 11 #define ICLK_MASK 0x00000080 12 #define PLLDIV_MASK 0x00000007 13 #define CUROSC_MASK 0x00000007 14 #define PLLMUL_MASK 0x0000007F 15 #define PB_MASK 0x00000007 16 #define FRC1 0 24 #define OSCCON 0x0000 25 #define SPLLCON 0x0020 26 #define PB1DIV 0x0140 30 u32 osc_freq = 0; in pic32_get_sysclk() [all …]
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/openbmc/linux/scripts/ |
H A D | extract_xc3028.pl | 25 my $debug=0; 50 while ($length > 0) { 66 my $msb = ($val >> 8) &0xff; 67 my $lsb = $val & 0xff; 75 my $l3 = ($val >> 24) & 0xff; 76 my $l2 = ($val >> 16) & 0xff; 77 my $l1 = ($val >> 8) & 0xff; 78 my $l0 = $val & 0xff; 87 my $l7 = ($msb_val >> 24) & 0xff; 88 my $l6 = ($msb_val >> 16) & 0xff; [all …]
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/openbmc/linux/arch/x86/kernel/cpu/ |
H A D | scattered.c | 27 { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, 28 { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, 29 { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 }, 30 { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 }, 31 { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 }, 32 { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 }, 33 { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 }, 34 { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 }, 35 { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 }, 36 { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_4_0_sh_mask.h | 26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000 28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001 30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL 31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002 32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL 33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L 35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006 [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/ |
H A D | cl837d.h | 28 #define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0… 29 #define NV837D_SOR_SET_CONTROL_OWNER 3:0 30 #define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) 31 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) 32 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) 34 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) 35 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) 36 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) 37 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) 39 #define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) [all …]
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | nvidia,tegra30-emc.yaml | 35 const: 0 53 "^emc-timings-[0-9]+$": 62 "^timing-[0-9]+$": 75 minimum: 0 91 Mode Register 0. 98 minimum: 0 239 reg = <0x7000f400 0x400>; 240 interrupts = <0 78 4>; 247 #interconnect-cells = <0>; 255 nvidia,emc-auto-cal-interval = <0x001fffff>; [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_1_0_sh_mask.h | 26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L 27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c 28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L 29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004 30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L 31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014 32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L 33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018 34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L 35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 [all …]
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