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Searched +full:0 +full:x0000000080000000 (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml144 reg = <0x0 0x7d500000 0x9310>;
152 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
153 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
154 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
155 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
156 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
160 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
161 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
162 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
164 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
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/openbmc/linux/arch/s390/boot/
H A Dhead_kdump.S11 #define DATAMOVER_ADDR 0x4000
12 #define COPY_PAGE_ADDR 0x6000
26 basr %r13,0
29 lg %r2,0(%r2) # already relocated:
32 lghi %r2,0 # Yes: Start kdump kernel
37 lg %r2,0x418(%r4) # Get kdump base
38 lg %r3,0x420(%r4) # Get kdump size
42 mvc 0(256,%r8),0(%r10) # Copy data mover code
45 mvc 0(256,%r8),0(%r10) # reserved mem
59 basr %r13,0 # Base
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/openbmc/linux/arch/powerpc/include/asm/
H A Dfirmware.h17 #define FW_FEATURE_PFT ASM_CONST(0x0000000000000001)
18 #define FW_FEATURE_TCE ASM_CONST(0x0000000000000002)
19 #define FW_FEATURE_SPRG0 ASM_CONST(0x0000000000000004)
20 #define FW_FEATURE_DABR ASM_CONST(0x0000000000000008)
21 #define FW_FEATURE_COPY ASM_CONST(0x0000000000000010)
22 #define FW_FEATURE_ASR ASM_CONST(0x0000000000000020)
23 #define FW_FEATURE_DEBUG ASM_CONST(0x0000000000000040)
24 #define FW_FEATURE_TERM ASM_CONST(0x0000000000000080)
25 #define FW_FEATURE_PERF ASM_CONST(0x0000000000000100)
26 #define FW_FEATURE_DUMP ASM_CONST(0x0000000000000200)
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H A Dcputable.h21 PPC_PMC_DEFAULT = 0,
77 * if the error is fatal, 1 if it was fully recovered and 0 to
111 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
112 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
113 #define CPU_FTR_DBELL ASM_CONST(0x00000004)
114 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
115 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
116 // ASM_CONST(0x00000020) Free
117 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
118 #define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
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/openbmc/linux/arch/parisc/kernel/
H A Dperf.c64 { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
68 { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
72 { 19, 1, 8 }, /* RDR 0 */
74 { 72, 2, 0 }, /* RDR 2 */
75 { 81, 2, 0 }, /* RDR 3 */
76 { 328, 6, 0 }, /* RDR 4 */
77 { 160, 3, 0 }, /* RDR 5 */
78 { 336, 6, 0 }, /* RDR 6 */
79 { 164, 3, 0 }, /* RDR 7 */
80 { 0, 0, 0 }, /* RDR 8 */
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/openbmc/u-boot/board/qualcomm/dragonboard820c/
H A Dreadme.txt32 4) generate fake, empty ramdisk (can have 0 bytes)
46 --base 0x80000000 \
80 -a 0x80080000 \
81 -e 0x80080000 \
105 ip=dhcp consoleblank=0 \
108 earlyprintk earlycon=msm_serial_dm,0x75b0000 \
132 S - Boot Config @ 0x00076044 = 0x000001c9
133 S - JTAG ID @ 0x000760f4 = 0x4003e0e1
134 S - OEM ID @ 0x000760f8 = 0x00000000
135 S - Serial Number @ 0x00074138 = 0x2e8844ce
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/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dreg.h13 asm volatile("mfspr %0," _str(rn) \
15 #define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
27 #define MMCR0_PMAO 0x00000080
28 #define MMCR0_PMAE 0x04000000
29 #define MMCR0_FC 0x80000000
35 #define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */
38 #define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */
39 #define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */
54 #define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
55 #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
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/openbmc/linux/arch/s390/include/uapi/asm/
H A Dptrace.h19 #define PT_PSWMASK 0x00
20 #define PT_PSWADDR 0x04
21 #define PT_GPR0 0x08
22 #define PT_GPR1 0x0C
23 #define PT_GPR2 0x10
24 #define PT_GPR3 0x14
25 #define PT_GPR4 0x18
26 #define PT_GPR5 0x1C
27 #define PT_GPR6 0x20
28 #define PT_GPR7 0x24
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/openbmc/linux/arch/sparc/kernel/
H A Dpci_sabre.c32 #define SABRE_UE_AFSR 0x0030UL
33 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
34 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
35 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
36 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
37 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
38 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
39 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
40 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
41 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
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/openbmc/qemu/target/s390x/
H A Dioinst.c28 * control structures are always starting at offset 0 and are in get_address_from_regs()
29 * always aligned and accessible. So we can return 0 here which in get_address_from_regs()
33 *ar = 0; in get_address_from_regs()
34 return 0; in get_address_from_regs()
49 *cssid = 0; in ioinst_disassemble_sch_ident()
50 *m = 0; in ioinst_disassemble_sch_ident()
57 return 0; in ioinst_disassemble_sch_ident()
118 return 0; in ioinst_schib_valid()
122 return 0; in ioinst_schib_valid()
124 /* for MB format 1 bits 26-31 of word 11 must be 0 */ in ioinst_schib_valid()
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/openbmc/u-boot/doc/
H A DREADME.sifive-fu54069 Hit any key to stop autoboot: 0
73 riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
88 boot_params = 0x0000000000000000
89 DRAM bank = 0x0000000000000000
90 -> start = 0x0000000080000000
91 -> size = 0x0000000200000000
92 relocaddr = 0x00000000fff90000
93 reloc off = 0x000000007fd90000
98 ethernet@10090000: PHY present at 0
101 ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3800)
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/openbmc/linux/drivers/infiniband/hw/qib/
H A Dqib_7322_regs.h35 #define QIB_7322_Revision_OFFS 0x0
36 #define QIB_7322_Revision_DEF 0x0000000002010601
37 #define QIB_7322_Revision_R_Simulator_LSB 0x3F
38 #define QIB_7322_Revision_R_Simulator_MSB 0x3F
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7322_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7322_Revision_R_Emulation_MSB 0x3E
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
43 #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
44 #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
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/openbmc/qemu/target/arm/
H A Dhelper.c126 for (i = 0; i < cpu->cpreg_array_len; i++) { in write_cpustate_to_list()
171 for (i = 0; i < cpu->cpreg_array_len; i++) { in write_list_to_cpustate()
233 return 0; in cpreg_key_compare()
248 cpu->cpreg_array_len = 0; in init_cpreg_list()
258 cpu->cpreg_array_len = 0; in init_cpreg_list()
280 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
449 * writes, so only needs to apply to NS PL1&0, not S PL1&0. in alle1_tlbmask()
593 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); in tlbimva_hyp_write()
602 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); in tlbimva_hyp_is_write()
612 uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; in tlbiipas2_hyp_write()
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